
Adam Peterson
• Six years of customer management experience – incl. tier 1 OEM international and domestic customers. • Twelve years of product... | San Jose, California, United States
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Adam Peterson’s Emails ad****@su****.net
Adam Peterson’s Phone Numbers No phone number available.
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Adam Peterson’s Location San Jose, California, United States
Adam Peterson’s Expertise • Six years of customer management experience – incl. tier 1 OEM international and domestic customers. • Twelve years of product development and Flash memory manufacturing experience • Proven effectiveness in managing small teams and meeting project schedules. • Solid foundation in all aspects of flash/SSD manufacturing, including fab, wafer test, assembly, package test, and Q&R.
Adam Peterson’s Current Industry Western Digital
Adam
Peterson’s Prior Industry
Intel
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Pny Technologies
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Sandisk
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Western Digital
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Work Experience

Western Digital
Director QAPM
Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Western Digital
Director Customer Quality Management
Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Sandisk
Director CSS Customer Quality
Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Pny Technologies
Director of Quality and Reliability, Storage Solutions
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Customer Quality Engineer
Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Manufacturing Engineering Manager
Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Manufacturing Improvements Engineer
Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Wafer Sort Group Team Leader
Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Product Engineer
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)