Adarsh Santhosh
Senior DFT Engineer. Skilled in below topics. Design for test: Spyglass, MBIST, SCAN, ATPG (SAF, TDF, IDDQ), Test constraints... | Bengaluru, Bengaluru, India
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Adarsh Santhosh’s Emails as****@qu****.com
Adarsh Santhosh’s Phone Numbers 1858651****
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Adarsh Santhosh’s Location Bengaluru, Bengaluru, India
Adarsh Santhosh’s Expertise Senior DFT Engineer. Skilled in below topics. Design for test: Spyglass, MBIST, SCAN, ATPG (SAF, TDF, IDDQ), Test constraints & STA, Formal verification, Silicon Bring up and debug. Design verification: System Verilog, UVM, Assertion based verification. Digital logic circuit design: TAP, Boundary Scan, IJTAG, OCC, Stream Scan Network, LPCT, Test point insertion, LBIST. Scripting: Python, Linux, C++, vim, Tcl.
Adarsh Santhosh’s Current Industry Qualcomm
Adarsh
Santhosh’s Prior Industry
Test And Verification Solutions
|
Stmicroelectronics
|
Amd
|
Tessolve
|
Qualcomm
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Work Experience
Qualcomm
Dft Engineer
Mon Jun 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Tessolve
Dft Engineer
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Dft Engineer
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Dft & Verification Engineer
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Test And Verification Solutions
Dft Engineer
Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Adarsh Santhosh Email Addresses
Adarsh Santhosh Phone Number
FAQ About Adarsh Santhosh
-
Adarsh Santhosh is located at
Bengaluru, Bengaluru, India -
Adarsh Santhosh is a
Senior DFT Engineer. Skilled in below topics. Design for test: Spyglass, MBIST, SCAN, ATPG (SAF, TDF, IDDQ), Test constraints & STA, Formal verification, Silicon Bring up and debug. Design verification: System Verilog, UVM, Assertion based verification. Digital logic circuit design: TAP, Boundary Scan, IJTAG, OCC, Stream Scan Network, LPCT, Test point insertion, LBIST. Scripting: Python, Linux, C++, vim, Tcl. Qualcomm -
Adarsh Santhosh currently works in the
Qualcomm -
Adarsh Santhosh specializes in
Senior DFT Engineer. Skilled in below topics. Design for test: Spyglass, MBIST, SCAN, ATPG (SAF, TDF, IDDQ), Test constraints & STA, Formal verification, Silicon Bring up and debug. Design verification: System Verilog, UVM, Assertion based verification. Digital logic circuit design: TAP, Boundary Scan, IJTAG, OCC, Stream Scan Network, LPCT, Test point insertion, LBIST. Scripting: Python, Linux, C++, vim, Tcl. -
Adarsh Santhosh speaks the following languages:
No languages available. -
Adarsh Santhosh has prior experience in the following industries:
Tessolve , Amd , Stmicroelectronics , Test And Verification Solutions -
Adarsh Santhosh has the following professional experience:
Qualcomm , Tessolve , Amd , Stmicroelectronics , Test And Verification Solutions . -
You can view Adarsh Santhosh’s
LinkedIn profile at LinkedIn URL. -
Adarsh Santhosh’s work email addresses are
[email protected] . -
Adarsh Santhosh works at
Qualcomm
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