Ahmad Sagir
professional skilled in Floor planning Full chip, coordinate between all Designers and Physical designers ,... | Haifa, Haifa District, Israel
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Ahmad Sagir’s Location Haifa, Haifa District, Israel
Ahmad Sagir’s Expertise professional skilled in Floor planning Full chip, coordinate between all Designers and Physical designers , creating the Power Grid on all chip ( multi power Domains) , Planning Bump out and coordinate with Package team to make the Bump Out Ideal for the Package routing of the Sensitive I/O Bumps ( TX/RX Bumps). running and fixing IR Drop and EM (Totem, Voltus Tools) , HV Layout Design, all kinds of Layout verifications like DRC/ANT/DEN/ERC/MRC/DFM, Analog Circuit Design, CMOS, and Layout Vs Schematic (LVS). Tools ---------------------------- Cadence: Virtuoso-L/XL/GXL and EXL version 20+ PVS, Assura, Dracula, Diva, ModGen, Constraint Manager MMSIM, Spectre, Schematic designer, and etc. Field for Bumps and Die files Creation. Mentor Graphics: Pyxis, IC station, Calibre, Calibre RVE, Cilibre DRV. Synopsys: Laker, Custom Designer, Hercules, HSpice, in-house verification tools and etc. All internal Intel layout, RV and ckt Tools Technology Worked: ---------------------------- TSMC: 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 16nm . Intel : all processes 65nm -- 10nm .
Ahmad Sagir’s Current Industry Intel
Ahmad
Sagir’s Prior Industry
Intel
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Work Experience
Intel
Senior Layout Designer , Rf Full Chip Tichnical Leader
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Manager
Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Full Chip Layout Designer , Floor Plan And Top Level Integrator
Mon Sep 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Senior Physical Designer Specializing In Top Level Analog Layout.
Mon Sep 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Design Engineering
Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Layout Designer , Rf Full Chip Tichnical Leader
— PresentSkills
Languages
Ahmad Sagir Email Addresses
FAQ About Ahmad Sagir
-
Ahmad Sagir is located at
Haifa, Haifa District, Israel -
Ahmad Sagir is a
professional skilled in Floor planning Full chip, coordinate between all Designers and Physical designers , creating the Power Grid on all chip ( multi power Domains) , Planning Bump out and coordinate with Package team to make the Bump Out Ideal for the Package routing of the Sensitive I/O Bumps ( TX/RX Bumps). running and fixing IR Drop and EM (Totem, Voltus Tools) , HV Layout Design, all kinds of Layout verifications like DRC/ANT/DEN/ERC/MRC/DFM, Analog Circuit Design, CMOS, and Layout Vs Schematic (LVS). Tools ---------------------------- Cadence: Virtuoso-L/XL/GXL and EXL version 20+ PVS, Assura, Dracula, Diva, ModGen, Constraint Manager MMSIM, Spectre, Schematic designer, and etc. Field for Bumps and Die files Creation. Mentor Graphics: Pyxis, IC station, Calibre, Calibre RVE, Cilibre DRV. Synopsys: Laker, Custom Designer, Hercules, HSpice, in-house verification tools and etc. All internal Intel layout, RV and ckt Tools Technology Worked: ---------------------------- TSMC: 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 16nm . Intel : all processes 65nm -- 10nm . Intel -
Ahmad Sagir currently works in the
Intel -
Ahmad Sagir specializes in
professional skilled in Floor planning Full chip, coordinate between all Designers and Physical designers , creating the Power Grid on all chip ( multi power Domains) , Planning Bump out and coordinate with Package team to make the Bump Out Ideal for the Package routing of the Sensitive I/O Bumps ( TX/RX Bumps). running and fixing IR Drop and EM (Totem, Voltus Tools) , HV Layout Design, all kinds of Layout verifications like DRC/ANT/DEN/ERC/MRC/DFM, Analog Circuit Design, CMOS, and Layout Vs Schematic (LVS). Tools ---------------------------- Cadence: Virtuoso-L/XL/GXL and EXL version 20+ PVS, Assura, Dracula, Diva, ModGen, Constraint Manager MMSIM, Spectre, Schematic designer, and etc. Field for Bumps and Die files Creation. Mentor Graphics: Pyxis, IC station, Calibre, Calibre RVE, Cilibre DRV. Synopsys: Laker, Custom Designer, Hercules, HSpice, in-house verification tools and etc. All internal Intel layout, RV and ckt Tools Technology Worked: ---------------------------- TSMC: 130nm, 90nm, 65nm, 45nm, 28nm, 22nm, 16nm . Intel : all processes 65nm -- 10nm . -
Ahmad Sagir speaks the following languages:
No languages available. -
Ahmad Sagir has prior experience in the following industries:
Intel , Intel , Intel -
Ahmad Sagir has the following professional experience:
Intel , Intel , Intel , Intel , Intel , Intel . -
You can view Ahmad Sagir’s
LinkedIn profile at LinkedIn URL. -
Ahmad Sagir’s work email addresses are
[email protected] . -
Ahmad Sagir works at
Intel
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