
Ahmed Yehia
• Emulation and FPGA Prototyping o High performance TLM modeling for Emulation acceleration (UVM acceleration, C/C++,... | 6917 Gabion Drive, Austin, United States
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Ahmed Yehia’s Location 6917 Gabion Drive, Austin, United States
Ahmed Yehia’s Expertise • Emulation and FPGA Prototyping o High performance TLM modeling for Emulation acceleration (UVM acceleration, C/C++, SCEMI pipes) o Verification continuum from Simulation to Emulation and FPGA prototyping o Virtual prototyping (Android/Linux benchmarking on Hybrid Emulation platforms) o Emulation and FPGA prototyping performance optimizations (Synthesis/compile frequency, runtime throughput, turn-around time, time to waveforms). • ASIC/FPGA Digital Design and Functional Verification o Constrained Random/Metric Driven Verification using SystemVerilog, UVM/OVM, Specman-e/eRM. o Assertion Based Verification using SystemVerilog Assertions (SVA). o Logic design using VHDL, Verilog and SystemVerilog. o Simulation performance optimizations and RTL/Gate level functional/timing simulation and Debug. • Low power design and verification o Power strategy definition, verification, simulation and debug using IEEE Unified Power Format (UPF) standard. o Power Analysis on RTL and GLE in Simulation/Emulation w/ Power analysis tools (PowerArtist, PowerPro) • On-chip protocols (e.g. AMBA ACE/AXI/AHB/APB). Off-chip protocols (e.g. JTAG, UART, SPI, DDR). • Verification Management and Coverage closure using Accellera Unified Coverage Interoperability Standard (UCIS). • Software Testing & Verification o Black box, white box, negative, Performance/stress, Interactive testing, and test automation. • Platforms: Linux/Unix, SGE/Univa, LSF. • Programming o Shell scripting (Csh, Ksh/Bash), Perl, Python, Tcl, Make, R, C/C++, Java, Android. • Tooling o EDA - Hardware: Veloce/Strato, Veloce Prototyping System (VPS), Zebu Emulation platform o EDA - Software: Questa/Modelsim, VCS, Specman, Verdi, Veloce HYCON, Veloce TBX, Veloce/Questa VIP, Xilinx Vivado, Altera Quartus, Codelink, Questa Infact, Questa CoverCheck, Questa Visualizer o System Level design: Matlab o Source Code Control: Perforce, Git, CVS, Clearcase
Ahmed Yehia’s Current Industry Apple
Ahmed
Yehia’s Prior Industry
Mentor Graphics
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Apple
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Work Experience

Apple
Design Verification Engineer
Wed Jan 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mentor Graphics
Senior Emulation/FPGA Prototyping Engineer
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Mentor Graphics
Functional Verification Technologist
Sun May 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)