
Akash Sharma
Integrated Circuit Design: • Design of LDO regulators, OP-AMPs, analog buffers, bandgap reference, current bias, feedback and... | Santa Clara, California, United States
*50 free lookup(s) per month.
No credit card required.
Akash Sharma’s Emails ak****@fr****.com
Akash Sharma’s Phone Numbers No phone number available.
Social Media
Akash Sharma’s Location Santa Clara, California, United States
Akash Sharma’s Expertise Integrated Circuit Design: • Design of LDO regulators, OP-AMPs, analog buffers, bandgap reference, current bias, feedback and compensation techniques. • Pre and post layout simulations for pre-silicon verification of the designed blocks across PVT and monte-carlo simulations. • Top-level verification of the IC using Verilog and Verilog AMS. Hardware Design • Characterization of Analog and Mixed signal ICs for automotive application and consumer products (PMICs) • Closely worked with the Apps Engineers, Product Engineers and ATE team to successfully evaluate the ICs. • Development of evaluation boards and software applications (LabVIEW GUI), Component Selection, Schematic Entry, Circuit Simulation, PCB Layout, Signal Routing, BOM Creation, Board bring up, Test plan preparation and Firmware integration. • Development of NI LabVIEW application and TestStand sequences to fully automate the characterization of ICs
Akash Sharma’s Current Industry Nvidia
Akash
Sharma’s Prior Industry
Ibm Global Business Services
|
Arizona State University
|
Freescale Semiconductor
|
Nxp Acquires Freescale Semiconductor
|
Nxp Semiconductors
|
Nvidia
Not the Akash Sharma you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Nvidia
System Design Engineer (Automotive Hardware)
Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Nxp Semiconductors
Hardware Design Engineer
Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Acquires Freescale Semiconductor
Rotation Engineer (Analog-Mixed Signal Design)
Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Freescale Semiconductor
Analog Design Engineer (Intern)
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Arizona State University
Research Aide
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm Global Business Services
System Engineer
Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)