Amit Jarika
• Responsible for RTL to GDS flow for a block in 7nm technology node for Silicon Engineering... | Bengaluru, Karnataka, India
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Amit Jarika’s Emails am****@am****.com
Amit Jarika’s Phone Numbers No phone number available.
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Amit Jarika’s Location Bengaluru, Karnataka, India
Amit Jarika’s Expertise • Responsible for RTL to GDS flow for a block in 7nm technology node for Silicon Engineering Group. • Handling LVS ,LEC checks,IREM analysis for a block. • Fixing timing and DRC violations. • Scripting in Tcl and Python. • Completed M.tech in VLSI Design from N.I.T Nagpur. I have experienced in Verilog, Hands on various EDA Tools, RTL Verification, RTL to GDS flow. Final year project: TCAD Simulation of non volatile memory based on Organic Field Effect Transistors.
Amit Jarika’s Current Industry Ampere
Amit
Jarika’s Prior Industry
Visvesvaraya National Institute Of Technology
|
Ampere
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Work Experience
Ampere
Physical Design Engineer I
Wed Apr 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Ampere
Design Engineer I
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Ampere
Physical Design Intern
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Visvesvaraya National Institute Of Technology
Teaching Assistant (Part Of Curriculum)
Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
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Amit Jarika Email Addresses
FAQ About Amit Jarika
-
Amit Jarika is located at
Bengaluru, Karnataka, India -
Amit Jarika is a
• Responsible for RTL to GDS flow for a block in 7nm technology node for Silicon Engineering Group. • Handling LVS ,LEC checks,IREM analysis for a block. • Fixing timing and DRC violations. • Scripting in Tcl and Python. • Completed M.tech in VLSI Design from N.I.T Nagpur. I have experienced in Verilog, Hands on various EDA Tools, RTL Verification, RTL to GDS flow. Final year project: TCAD Simulation of non volatile memory based on Organic Field Effect Transistors. Ampere -
Amit Jarika currently works in the
Ampere -
Amit Jarika specializes in
• Responsible for RTL to GDS flow for a block in 7nm technology node for Silicon Engineering Group. • Handling LVS ,LEC checks,IREM analysis for a block. • Fixing timing and DRC violations. • Scripting in Tcl and Python. • Completed M.tech in VLSI Design from N.I.T Nagpur. I have experienced in Verilog, Hands on various EDA Tools, RTL Verification, RTL to GDS flow. Final year project: TCAD Simulation of non volatile memory based on Organic Field Effect Transistors. -
Amit Jarika speaks the following languages:
No languages available. -
Amit Jarika has prior experience in the following industries:
Ampere , Ampere , Ampere , Visvesvaraya National Institute Of Technology -
Amit Jarika has the following professional experience:
Ampere , Ampere , Ampere , Visvesvaraya National Institute Of Technology . -
You can view Amit Jarika’s
LinkedIn profile at LinkedIn URL. -
Amit Jarika’s work email addresses are
[email protected] . -
Amit Jarika works at
Ampere
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