
Amith Sudarshan
Digital IC Design and Verification Engineer with following skills set: - Langauges : Verilog, System Verilog, UVM, PERL, Python -... | Chandler, Arizona, United States
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Amith Sudarshan’s Emails am****@ar****.com
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Amith Sudarshan’s Location Chandler, Arizona, United States
Amith Sudarshan’s Expertise Digital IC Design and Verification Engineer with following skills set: - Langauges : Verilog, System Verilog, UVM, PERL, Python - Verification skills : Testbench development, debug, analysis and enhancement of functional & code coverage, assertions, regressions handling - Architectures: arm A-class and M-class processors - Development and improvement of tool flows, scripts and methodologies - Well versed with Computer architecture concepts & AMBA AXI4 protocol - Good understanding of the Functional Safety process and flows - Tools : QuestaSim, ModelSim, SimVision, Design Vision & DVE, ARM tools
Amith Sudarshan’s Current Industry Arm
Amith
Sudarshan’s Prior Industry
Wipro
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Marvell Semiconductor
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Arm
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Work Experience

Arm
Staff Engineer
Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Arm
Senior Verification Engineer
Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Arm
Design and Verification Engineer
Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Marvell Semiconductor
Digital IC Design Engineer
Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Marvell Semiconductor
Engineering Intern - CPU team
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro
Project Engineer
Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)