
Anand Rk
Experienced Design Engineering Director with a demonstrated experience of working in the Semi Conductor industry. Skilled in silicon... | San Jose, California, United States
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Anand Rk’s Emails ar****@ca****.com
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Anand Rk’s Location San Jose, California, United States
Anand Rk’s Expertise Experienced Design Engineering Director with a demonstrated experience of working in the Semi Conductor industry. Skilled in silicon bringup, debug, validation and customer support of IEEE802.3 ETHERNET 112Gbps PAM4, 53Gbps PAM4, 25GKr, 10GKr, PCIe Gen4, CCIX, USB3.1 Gen1/2, MPHY G3, Verilog, LabVIEW, Field-Programmable Gate Arrays (FPGA), and Xilinx Vivado/ISE. Strong engineering professional with a Master's of Technology focused in Microelectronics form BITS, Pilani and Bachelor’s Degree focused in Applied Electronics and Instrumentation from College of Engineering, Trivandrum.
Anand Rk’s Current Industry Cadence Design Systems
Anand
Rk’s Prior Industry
Deloitte
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Cosmic Circuits
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Cadence Design Systems
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Work Experience

Cadence Design Systems
Design Engineering Director
Sat Jul 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cadence Design Systems
Sr Design Engineering Manager
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Design Engineering Manager
Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Principal Design Engineer
Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Lead Design Engineer
Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Design Engineer II
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Cosmic Circuits
Design Engineer
Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Deloitte
Business Analyst
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)