
Ankit Patel
14+ years of rich and diverse experience in the Physical Design (analog/mixed-signal IP and digital + ASIC... | San Francisco, California, United States
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Ankit Patel’s Emails an****@sy****.com
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Ankit Patel’s Location San Francisco, California, United States
Ankit Patel’s Expertise 14+ years of rich and diverse experience in the Physical Design (analog/mixed-signal IP and digital + ASIC domains) => Experience working with Foundry PPA R&D Team on 3nm , 18A and other advance nodes. => Experience in Applications Engineering (Pre sales + Technical Enablement + Implementation) with Tier 1 customers of Cadence on cutting edge physical design product INNOVUS (7nm, 5nm etc.) Block level and Chip Top. And also worked in Product Engineering (post sales - technical ) for all aspects of STA, Synthesis, Physical Design, Simulation for DDR/LPDDRY PHY IP. => Worked on cutting edge process technologies (22nm, 14nm and 10nm ) with Intel Corporation. Proficient in all aspects of Physical Design: Experience in Synthesis, Place and Route of Hard IP's specifically Low Power Memory Design (LPDDR4) used on SOC's - Tablets and Smartphones.
Ankit Patel’s Current Industry Intel
Ankit
Patel’s Prior Industry
Wipro Bps
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California State University Sacramento
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Novellus Systems Acquired By Lam Research
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Intel
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Cadence Design Systems
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Proteantecs
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Synopsys
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Work Experience

Intel
Application and Platform Solutions - Intel Foundry
Thu Feb 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Synopsys
Staff R&D Engineer
Mon Jun 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Proteantecs
Sr. Staff Application Engineer
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Applications Engineering Lead
Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Cadence Design Systems
Design IP Product Lead - DDR PHY
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Physical (Structural) Design Engineer
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Physical Design Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Novellus Systems Acquired By Lam Research
Design Intern - IC Manufacturing, PECVD
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
California State University Sacramento
Graduate Student Assistant
Sat Sep 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro Bps
Customer Support Engineer
Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)