Anudeep Kuppala

Staff Engineer with ~10 years of experience in Design verification and Validation of ICs. •Lead teams to verify... | Bengaluru, Karnataka, India

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Anudeep Kuppala’s Emails ak****@qu****.com

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Anudeep Kuppala’s Location Bengaluru, Karnataka, India

Anudeep Kuppala’s Expertise Staff Engineer with ~10 years of experience in Design verification and Validation of ICs. •Lead teams to verify multiple IP cores within a stipulated timeframe. •Implemented UVM Testbench from scratch with UVM_REG flow. •Worked extensively on test planning with directed/random tests, checks, coverages, etc. •Owned verification of multiple complex design features across various projects. •High aptitude for debugging. •Experience in developing test benches in UVM and System Verilog from scratch and and outlining test , coverage plans and gate sim. •Hands on Verification on SoundWire (MIPI), QMSPI,QSPI,Q2SPI,QUPV3 (UART,I2C,SPI etc) & Bus protocols ahb. •Master of Technology from IIIT-H, Hyderabad in VLSI & CE.

Anudeep Kuppala’s Current Industry Microsoft

Anudeep Kuppala’s Prior Industry
Microsemi | Qualcomm | Microsoft

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Work Experience

Microsoft

Senior Design Verification Engineer

Fri Sep 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Qualcomm

Staff Engineer

Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcomm

Senior Lead Engineer

Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcomm

Senior Engineer, Digital Design/Verification Engineer

Fri Jul 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Microsemi

Engineer-2, Characterization

Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Microsemi

Engineer-1, Characterization

Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Microsemi

intern

Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

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Anudeep Kuppala Email Addresses

ak****@qu****.com Work Email

ak****@qu****.com Personal Email

FAQ About Anudeep Kuppala

Anudeep Kuppala is located at
Bengaluru, Karnataka, India

Anudeep Kuppala is a
Staff Engineer with ~10 years of experience in Design verification and Validation of ICs. •Lead teams to verify multiple IP cores within a stipulated timeframe. •Implemented UVM Testbench from scratch with UVM_REG flow. •Worked extensively on test planning with directed/random tests, checks, coverages, etc. •Owned verification of multiple complex design features across various projects. •High aptitude for debugging. •Experience in developing test benches in UVM and System Verilog from scratch and and outlining test , coverage plans and gate sim. •Hands on Verification on SoundWire (MIPI), QMSPI,QSPI,Q2SPI,QUPV3 (UART,I2C,SPI etc) & Bus protocols ahb. •Master of Technology from IIIT-H, Hyderabad in VLSI & CE. Microsoft

Anudeep Kuppala currently works in the
Microsoft

Anudeep Kuppala specializes in
Staff Engineer with ~10 years of experience in Design verification and Validation of ICs. •Lead teams to verify multiple IP cores within a stipulated timeframe. •Implemented UVM Testbench from scratch with UVM_REG flow. •Worked extensively on test planning with directed/random tests, checks, coverages, etc. •Owned verification of multiple complex design features across various projects. •High aptitude for debugging. •Experience in developing test benches in UVM and System Verilog from scratch and and outlining test , coverage plans and gate sim. •Hands on Verification on SoundWire (MIPI), QMSPI,QSPI,Q2SPI,QUPV3 (UART,I2C,SPI etc) & Bus protocols ahb. •Master of Technology from IIIT-H, Hyderabad in VLSI & CE.