Araceli Varela-Safiri
A motivated and enthusiastic Analog/Mixed Signal/RF Custom Senior RFIC Layout Design engineer with 20 + year's experience. Extensive knowledge... | Irvine, California, United States
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Araceli Varela-Safiri’s Emails av****@go****.com
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Araceli Varela-Safiri’s Location Irvine, California, United States
Araceli Varela-Safiri’s Expertise A motivated and enthusiastic Analog/Mixed Signal/RF Custom Senior RFIC Layout Design engineer with 20 + year's experience. Extensive knowledge and successful experience with top-level floorplan, hookup and layout verification. Good understanding of layout techniques like matching, balancing nets, shielding, inter-digitating, common centroid, electron migration, latch-up. Hands on knowledge in working with analog layouts and top level routing for transceivers. Familiar with Cadence, Virtuoso XL, Calibre, Assura, Hercules, K2, PVS. Completed layout of Transceiver sub-blocks as (Baseband Filter, LNA Mixers, Oscillators, DAC, LDO, PLL’s, VCO, Clock Multiplier, Auxiliary Functions. ADC. Dividers, etc).
Araceli Varela-Safiri’s Current Industry Apple
Araceli
Varela-Safiri’s Prior Industry
Pi Designs On Silicon
|
Nvidia
|
Icera
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Sirific Wireles
|
Universal Cadworks
|
Texas Instruments
|
Goodix Technology
|
Apple
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Work Experience
Apple
RFIC Layout Engineer
Thu Dec 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Goodix Technology
Senior Staff Engineer
Wed Apr 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Senior RFIC Layout Design Engineer - WCS MCU Hardware Development
Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Universal Cadworks
Senior RFIC Layout Design Engineer Contracting at Texas Instruments Corp.
Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Nvidia
Senior RFIC Layout Design Engineer
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Icera
Senior RFIC Layout Design Engineer
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Sirific Wireles
Analog Layout Design Engineer
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Pi Designs On Silicon
ASIC Layout Designer.
Fri Dec 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Araceli Varela-Safiri Email Addresses
FAQ About Araceli Varela-Safiri
-
Araceli Varela-Safiri is located at
Irvine, California, United States -
Araceli Varela-Safiri is a
A motivated and enthusiastic Analog/Mixed Signal/RF Custom Senior RFIC Layout Design engineer with 20 + year's experience. Extensive knowledge and successful experience with top-level floorplan, hookup and layout verification. Good understanding of layout techniques like matching, balancing nets, shielding, inter-digitating, common centroid, electron migration, latch-up. Hands on knowledge in working with analog layouts and top level routing for transceivers. Familiar with Cadence, Virtuoso XL, Calibre, Assura, Hercules, K2, PVS. Completed layout of Transceiver sub-blocks as (Baseband Filter, LNA Mixers, Oscillators, DAC, LDO, PLL’s, VCO, Clock Multiplier, Auxiliary Functions. ADC. Dividers, etc). Apple -
Araceli Varela-Safiri currently works in the
Apple -
Araceli Varela-Safiri specializes in
A motivated and enthusiastic Analog/Mixed Signal/RF Custom Senior RFIC Layout Design engineer with 20 + year's experience. Extensive knowledge and successful experience with top-level floorplan, hookup and layout verification. Good understanding of layout techniques like matching, balancing nets, shielding, inter-digitating, common centroid, electron migration, latch-up. Hands on knowledge in working with analog layouts and top level routing for transceivers. Familiar with Cadence, Virtuoso XL, Calibre, Assura, Hercules, K2, PVS. Completed layout of Transceiver sub-blocks as (Baseband Filter, LNA Mixers, Oscillators, DAC, LDO, PLL’s, VCO, Clock Multiplier, Auxiliary Functions. ADC. Dividers, etc). -
Araceli Varela-Safiri speaks the following languages:
No languages available. -
Araceli Varela-Safiri has prior experience in the following industries:
Goodix Technology , Texas Instruments , Universal Cadworks , Nvidia , Icera , Sirific Wireles , Pi Designs On Silicon -
Araceli Varela-Safiri has the following professional experience:
Apple , Goodix Technology , Texas Instruments , Universal Cadworks , Nvidia , Icera , Sirific Wireles , Pi Designs On Silicon . -
You can view Araceli Varela-Safiri’s
LinkedIn profile at LinkedIn URL. -
Araceli Varela-Safiri’s work email addresses are
[email protected] . -
Araceli Varela-Safiri works at
Apple
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