Asaf Zecharya
Part of the cellular team at Marvell Israel. Full netlist to GDSII flow implementation (28nm). Specialties: Floor-planning, clock and power... | Israel
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Asaf Zecharya’s Location Israel
Asaf Zecharya’s Expertise Part of the cellular team at Marvell Israel. Full netlist to GDSII flow implementation (28nm). Specialties: Floor-planning, clock and power distribution, place & route, layout verification (DRC/LVS/ERC) and Timing closure. Experience with SoC practices such as Multiple power domain, Clock domains, Solve congestion issues. Work on Macro level and full chip Calibre physical verification. Experience with place & route tools – Cadence (Encounter) and Magma (Talus). Programming skills in: TCL, Cshell, Perl.
Asaf Zecharya’s Current Industry Intel
Asaf
Zecharya’s Prior Industry
Marvell
|
Intel
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Work Experience
Intel
Logic Design Engineer
Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Physical Design Engineer
Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Marvell
Backend (Physical Design) Engeenir.
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Asaf Zecharya Email Addresses
FAQ About Asaf Zecharya
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Asaf Zecharya is located at
Israel -
Asaf Zecharya is a
Part of the cellular team at Marvell Israel. Full netlist to GDSII flow implementation (28nm). Specialties: Floor-planning, clock and power distribution, place & route, layout verification (DRC/LVS/ERC) and Timing closure. Experience with SoC practices such as Multiple power domain, Clock domains, Solve congestion issues. Work on Macro level and full chip Calibre physical verification. Experience with place & route tools – Cadence (Encounter) and Magma (Talus). Programming skills in: TCL, Cshell, Perl. Intel -
Asaf Zecharya currently works in the
Intel -
Asaf Zecharya specializes in
Part of the cellular team at Marvell Israel. Full netlist to GDSII flow implementation (28nm). Specialties: Floor-planning, clock and power distribution, place & route, layout verification (DRC/LVS/ERC) and Timing closure. Experience with SoC practices such as Multiple power domain, Clock domains, Solve congestion issues. Work on Macro level and full chip Calibre physical verification. Experience with place & route tools – Cadence (Encounter) and Magma (Talus). Programming skills in: TCL, Cshell, Perl. -
Asaf Zecharya speaks the following languages:
No languages available. -
Asaf Zecharya has prior experience in the following industries:
Intel , Marvell -
Asaf Zecharya has the following professional experience:
Intel , Intel , Marvell . -
You can view Asaf Zecharya’s
LinkedIn profile at LinkedIn URL. -
Asaf Zecharya’s work email addresses are
[email protected] . -
Asaf Zecharya works at
Intel
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