
Aseem Maheshwari
• 15+ years of industry experience in all aspects of VLSI design, including ASIC and FPGA • Strong technical design and... | Milpitas, California, United States
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Aseem Maheshwari’s Emails am****@pa****.com
Aseem Maheshwari’s Phone Numbers No phone number available.
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Aseem Maheshwari’s Location Milpitas, California, United States
Aseem Maheshwari’s Expertise • 15+ years of industry experience in all aspects of VLSI design, including ASIC and FPGA • Strong technical design and technical leadership skills with a successful record of designing and verifying high-speed multi clock domain devices • Proven success in fostering productive working relationships, managing multiple, simultaneous tasks while leading and directing teams • Excellent communication and presentation skills Specialties: Verilog, SystemVerilog, VMM, OVM, VHDL, Cadence (Verisity) e, Vera/NTB, Verilog PLI, C, C++, Perl, Python, SVA, OVL, PSL, TestBuilder Synopsys DC, ICC, Primetime and VCS/DVE, Cadence NC-Verilog, (Verisity) Specman Elite and eAnalyzer, Xilinx Alliance Tools, Altera Quartus and MAX-Plus 2, Synplify, Denali Memory Models
Aseem Maheshwari’s Current Industry Meta
Aseem
Maheshwari’s Prior Industry
Immersive Technologies
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Intrinsix
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Texas Instruments
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Cavium Networks
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Lsi
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Palo Alto Networks
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Meta
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Work Experience

Meta
Silicon Engineering Manager
Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Palo Alto Networks
Sr. Principal Engineer, ASIC Engineering
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Palo Alto Networks
Sr. Manager, ASIC Engineering
Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Palo Alto Networks
Manager, ASIC Engineering
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Palo Alto Networks
Principal Engineer, ASIC DV
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Principal Verification Design Engineer
Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Cavium Networks
Principal Engineer
Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Design Verification Lead
Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Design Verification Engineer
Wed Oct 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Intrinsix
Design Engineer
Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Immersive Technologies
Design Engineer
Mon May 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)