Aseem Maheshwari

Aseem Maheshwari

• 15+ years of industry experience in all aspects of VLSI design, including ASIC and FPGA • Strong technical design and... | Milpitas, California, United States

*50 free lookup(s) per month.

No credit card required.

Aseem Maheshwari’s Emails

Aseem Maheshwari’s Phone Numbers

Social Media

Aseem Maheshwari’s Location

Aseem Maheshwari’s Expertise

Aseem Maheshwari’s Current Industry

Aseem Maheshwari’s Prior Industry

Not the Aseem Maheshwari you were looking for?

Find accurate emails & phone numbers for over 700M professionals.

Work Experience

Meta

Silicon Engineering Manager

Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Palo Alto Networks

Sr. Principal Engineer, ASIC Engineering

Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Palo Alto Networks

Sr. Manager, ASIC Engineering

Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Palo Alto Networks

Manager, ASIC Engineering

Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Palo Alto Networks

Principal Engineer, ASIC DV

Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Lsi

Principal Verification Design Engineer

Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Cavium Networks

Principal Engineer

Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Design Verification Lead

Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Texas Instruments

Design Verification Engineer

Wed Oct 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Intrinsix

Design Engineer

Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)

Immersive Technologies

Design Engineer

Mon May 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

No languages available.