br****@nv****.com & No phone number available.

Brian Schieck

PC board , Substrate, Padring and RDL design Specialties: negotiation | 535 Eleanor Place, Hayward, United States

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Brian Schieck’s Emails br****@nv****.com

Brian Schieck’s Phone Numbers No phone number available.

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Brian Schieck’s Location 535 Eleanor Place, Hayward, United States

Brian Schieck’s Expertise PC board , Substrate, Padring and RDL design Specialties: negotiation

Brian Schieck’s Current Industry Nvidia

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Work Experience

Nvidia

VLSI Hw Manager IV - Substrates and padring

Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Nvidia

VLSI Hw Manager III - Substrates and padring

Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Nvidia

Sr. Systems Engineer

Sun Jul 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)

Believe

Sr Systems Engineer

Thu Feb 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

3dfx

Sr Systems Eng

Sun Feb 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

MTS3 Graphics ASIC design

Sat Mar 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

MTS 3 Graphics Board design

Fri Sep 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

MTS 2 Graphics Board design

Wed Sep 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

Associate Eng. Tech. Graphics Board design

Sun Sep 01 1991 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

Engineering Tech. 4 Graphics Board Design

Fri Sep 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 1991 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

Manufacturing Engineering Tech. 4

Tue Sep 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time)

Kevex

Factory Engineer

Sat Jan 01 1983 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time)

Zernus

Design and Service Manager

Tue Jan 01 1980 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 1980 00:00:00 GMT+0000 (Coordinated Universal Time)

Realtime

Design and Service Manager

Sat Jan 01 1977 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 1979 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

Brian Schieck Email Addresses

br****@nv****.com Work Email

br****@nv****.com Personal Email

FAQ About Brian Schieck

Brian Schieck is located at
535 Eleanor Place, Hayward, United States

Brian Schieck is a
PC board , Substrate, Padring and RDL design Specialties: negotiation Nvidia

Brian Schieck currently works in the
Nvidia

Brian Schieck specializes in
PC board , Substrate, Padring and RDL design Specialties: negotiation

Brian Schieck speaks the following languages:
No languages available.

Brian Schieck has prior experience in the following industries:
Nvidia , Nvidia , Believe , 3dfx , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Kevex , Zernus , Realtime

Brian Schieck has the following professional experience:
Nvidia , Nvidia , Nvidia , Believe , 3dfx , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Sun Microsystems , Kevex , Zernus , Realtime .