
Calvin Nguyen
- 20+ years experience in ASIC high speed design involving SOC, FPGA design, high speed serial interface protocol...
3935 7 Trees BoulevardApartment R204, San Jose, United States
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Calvin Nguyen’s Emails [email protected]
Calvin Nguyen’s Phone Numbers No phone number available.
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Calvin Nguyen’s Location 3935 7 Trees BoulevardApartment R204, San Jose, United States
Calvin Nguyen’s Expertise - 20+ years experience in ASIC high speed design involving SOC, FPGA design, high speed serial interface protocol stack, and various processing engines used in disk drives, multimedia graphics and networking applications. - Designed Serial RapidIO, PCIe protocol stack. - Designed FPGA configuration NOC. - Designed accelerated 3D Graphics Engine, Processor designs. - Designed DMA Engine, and PCI interface. - Experienced with ASIC and SOC frontend designs using Verilog, System Verilog, VHDL. - Experienced with prototype design using Xilinx FPGA - Experienced with validation of SRIO interface designs. - Familiar with Python, TCL, Perl,.
Calvin Nguyen’s Current Industry Intel
Calvin
Nguyen’s Prior Industry
Ibm
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Alliance Semiconductor
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Neomagic
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Empowertel Networks
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Nazomi Communications
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Integrated Device Technology
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Altera
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Intel
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Work Experience

Intel
SoC Design Engineer
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Altera
Member of the Technical Staff
Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Integrated Device Technology
Staff Design Engineer
Fri Jul 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jul 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Nazomi Communications
Senior Design Engineer
Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Empowertel Networks
Senior Design Engineer
Fri Oct 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Neomagic
Senior Design Engineer
Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Alliance Semiconductor
Senior Design Engineer
Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Design Engineer
Sun Jan 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time)