
Cengiz Tunca
A self-motivated Digital ASIC and FPGA Design Engineer, with more than 23 years experience of digital design, verification,... | Carros, Carros, France
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Cengiz Tunca’s Emails ce****@se****.com
Cengiz Tunca’s Phone Numbers No phone number available.
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Cengiz Tunca’s Location Carros, Carros, France
Cengiz Tunca’s Expertise A self-motivated Digital ASIC and FPGA Design Engineer, with more than 23 years experience of digital design, verification, implementation and validation. Thriving on technical challenges with a proven track record of problem solving within various IC design stages including specification writing, RTL design, synthesis, STA and verification. A recognised proficient team member with first class interpersonal skills, who is capable of driving a multi-site team towards achieving challenging goals on time. Always looking for new challenges and keen on contributing in the development of the semiconductor industry. Specialties: STA (constraints development, timing closure) Synthesis (constraints development, optimisation) Verification (Specman, RTL & GL) Formal Proof (RTL-to-Gate & Gate-to-Gate) Digital Design (VHDL)
Cengiz Tunca’s Current Industry Schneider Electric
Cengiz
Tunca’s Prior Industry
Philips Semiconductors
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Texas Instruments
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St Ericsson
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Stmicroelectronics
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Infineon Technologies
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Mda
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Easii Ic
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Schneider Electric
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Work Experience

Schneider Electric
Senior ASIC and FPGA Contractor
Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Easii Ic
Senior STA Contractor
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Mda
Senior STA Contractor
Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Senior Verification Contractor
Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Senior Verification Contractor
Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Senior Verification Contractor
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Senior STA Contractor
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Senior Verification Contractor
Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Dec 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
St Ericsson
Senior STA Contractor
Fri May 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
STA Contractor
Sat Apr 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Philips Semiconductors
Principal Digital IC Design Eng.
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Philips Semiconductors
Senior Digital IC Design Eng.
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)