
Chetan Udawant
Hello, I'm Chetan, an electrical engineering graduate student at the San Jose State University. I've been working in verification... | San Jose, California, United States
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Chetan Udawant’s Emails ch****@sj****.edu
Chetan Udawant’s Phone Numbers No phone number available.
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Chetan Udawant’s Location San Jose, California, United States
Chetan Udawant’s Expertise Hello, I'm Chetan, an electrical engineering graduate student at the San Jose State University. I've been working in verification domain from past 4 years. I'm actively seeking Verification engineer position. I have solid understanding and strong background of digital logic design, computer architecture, and good hands on experience with SystemVerilog and UVM, hands on experience with coding, scripting. I've played major role in the successful development of 6 complex Interface Verification IP (VIP) from scratch using SystemVerilog and UVM. Strong knowledge of AMBA APB, AHB, AHB-Lite, AXI4 and AXI4 Lite Interface Verification IP (VIP). SKILLS: • Programming Languages: SystemVerilog, SV Assertions, Verilog, C++, Assembly Language • Verification Methodology: Universal Verification Methodology (UVM) • Scripting languages: C shell, Perl, Python • Bus protocols: IMG BUS v1, v2 and v3, AMBA APB3 and APB4, AHB, AHB-Lite, AXI4 and AXI4-Lite • Operating systems: Linux and Windows • Tools: Cadence IES, IVB, Vmanager, Eplanner, Simvision, ncsim, DVT eclipse, Synopsys VCS, ncverilog, ModelSim PROFESSIONAL TRAINNINGS: • SystemVerilog language for verification (Cadence India.) • SystemVerilog Advanced Verification using UVM 1.1 (Cadence India.) • SystemVerilog Assertions (Cadence India.) Contact Info: E-mail ID: [email protected] Contact No: +1-669-238-6641
Chetan Udawant’s Current Industry Nvidia
Chetan
Udawant’s Prior Industry
Imagination Technologies
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Seagate Technology
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San Jose State University
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Intel
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Microsoft
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Google
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Amazon
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Nvidia
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Work Experience

Nvidia
Senior Design Verification Engineer
Mon Apr 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amazon
Design Verification Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
ASIC Design Verification Engineer
Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Microsoft
Design Verification Engineer 2
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
SoC Design Verification Engineer
Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Graduate Technical Intern
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Instructional Student Assistant
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Seagate Technology
ASIC Verification Engineering Intern
Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Imagination Technologies
Graduate Hardware Engineer - VLSI
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)