Chwei-Po Chew

Chwei-Po Chew

Specialties: Analog/Mixed signal design for high speed communication applications such as PLLs, SERDES | Cupertino, California, United States

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Work Experience

Lattice Semiconductor

Analog Designer

Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Silicon Image

MTS

Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Cypress Semiconductor

Senior staff design engineer

Sun Apr 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

National Semiconductor

Staff design engineer

Mon May 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

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