
Cj Kim
Extensive industry experience from architect to mass production in SoC and ASIC design fields with core proficiency in... | San Jose, California, United States
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Cj Kim’s Emails cj****@sk****.com
Cj Kim’s Phone Numbers No phone number available.
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Cj Kim’s Location San Jose, California, United States
Cj Kim’s Expertise Extensive industry experience from architect to mass production in SoC and ASIC design fields with core proficiency in ARM core and AMBA (APB/AHB/AXI) based multi-clock and multi-power domain design, top level integration, RTL design, LINT, CDC, synthesis, LEC, FPGA and silicon bring-up, functional verification, IP managing, and interaction with cross functional teams. Specialties: - PCIE-based Solid State Drive (SSD) Controller SoC. - ARM core and AMBA (APB/AHB/AXI) based SoC design. - Top level integration for IP connectivity. - ARM NIC400 (bus fabric) configuration and generation, RTL coding, CDC, LINT, functional verification, ECO, synthesis, LEC, STA, gate-level simulation, and ATE test support. - Post silicon bring-up, ES/CS/MS stage qualification issue debugging, mass production support. - Strong understanding of overall ASIC and SoC design flow from architecture to mass production. - Design Languages: Verilog, VHDL, Assembly, C-Shell, C/C++, Unix, Tcl, and Python. - EDA Tools: ARM Socrates, AMBA Designer, Spyglass, Design Compiler, PrimeTime, NCSim, Formality, Synplify Pro, Xilinx ISE, and etc.
Cj Kim’s Current Industry Samsung Semiconductor
Cj
Kim’s Prior Industry
Samsung Electronics
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Nethra Imaging
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Marvell Semiconductor
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Sk Hynix Memory Solutions America
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Solidigm
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Samsung Semiconductor
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Work Experience

Samsung Semiconductor
Principal Engineer
Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Solidigm
Principal Engineer
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Sk Hynix Memory Solutions America
Sr. Principal Engineer
Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Marvell Semiconductor
Digital Design Staff Engineer/Manager
Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Nethra Imaging
ASIC Design Engineer
Sat Dec 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung Electronics
ASIC and Soc Design Engineer
Tue Jul 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)