Darshan Alagud

Darshan Alagud

Currently involved in designing and writing micro-architecture specifications for components of a next generation On-Chip Interconnect. My work experience... | Austin, Texas, United States

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Work Experience

Arteris Ip

Staff Design Engineer - Interconnect

Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Arterisip

Sr. Design Engineer - Interconnect

Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Samsung Electronics

Sr. Design Engineer

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Oct 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Nxp Semiconductors

Design Engineer

Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Freescale Semiconductor

Logic Design Engineer

Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Grad Intern

Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Wipro Technologies

Project Engineer (VLSI)

Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)

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