Deepak Garg
A Blend of StrongTechnical Competencies with Good Business Sense (MBA in International business from IIFT Delhi) and understanding... | Bengaluru, Karnataka, India
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Deepak Garg’s Location Bengaluru, Karnataka, India
Deepak Garg’s Expertise A Blend of StrongTechnical Competencies with Good Business Sense (MBA in International business from IIFT Delhi) and understanding of the Semiconductor Industry (BTech from NIT Warangal) with 22+ Years of Experience of Full ASIC Cycle. Having & Nurturing Portfolio of Constraints & Power Team & Signoff STA as proven Leaders. Good FE/DV fundamentals help me to drive BU with Correct by Construction Approach aiming Zero defect (FTSS) silicon with Competitive PPA. Leading & Managing Design & Signoff with Developing with various check and Conceptualizing Strategy for a. PPA optimization. b. Execution Efficiency with Correct by Construction Approach. c. Quality (Zero re-work) due to quality misses in intermediate milestone. d. Zero Post Silicon Bugs in Signoff e. Created A Captive teams from ground zero to operational excellence. Technical Expertise : (07nm,10nm,14nm,28nm,40nm,65nm implementation) Leading an Implementation team for RTL to SIGNOFF Flow. Seasoned in SOC Planning & Architectural requirements leading Execution plan via milestones. Expert in Driving Clock Strategy for SOC & Budget Techniques. Expert in Driving Power Requirements and strategy for SOC/SS. Expert in SoC Signoff Static Timing Analysis, Clock Management, DFX Concept & Mitigation Plan Formulating STA Strategies and Risk Management. Good Cross-functional Coordination and Mentoring. Managed SoC integration, Subsystem developement Managed Silicon Vadilation support. Had hands on IP and SOC verification, Emulation platform using Axis n specman. Extensively worked on high definition Set Top Box . 28+ APSOC Tapped out with Good Success record.
Deepak Garg’s Current Industry Intel
Deepak
Garg’s Prior Industry
Intel
|
Lecturer Adhoc Faculty Of Nit Jaipur And Gyan Vihar University
|
Wipro Technologies
|
St Microelectronics
|
Qualcomm
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Work Experience
Intel
Sr Engineering Manager
Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Senior Staff Engineer
Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
St Microelectronics
Senior Staff Engineer/Manager
Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro Technologies
Vlsi Design Engineer
Wed May 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Lecturer Adhoc Faculty Of Nit Jaipur And Gyan Vihar University
Lecturer
Mon Oct 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Engineering Manager
— PresentSkills
Languages
Deepak Garg Email Addresses
FAQ About Deepak Garg
-
Deepak Garg is located at
Bengaluru, Karnataka, India -
Deepak Garg is a
A Blend of StrongTechnical Competencies with Good Business Sense (MBA in International business from IIFT Delhi) and understanding of the Semiconductor Industry (BTech from NIT Warangal) with 22+ Years of Experience of Full ASIC Cycle. Having & Nurturing Portfolio of Constraints & Power Team & Signoff STA as proven Leaders. Good FE/DV fundamentals help me to drive BU with Correct by Construction Approach aiming Zero defect (FTSS) silicon with Competitive PPA. Leading & Managing Design & Signoff with Developing with various check and Conceptualizing Strategy for a. PPA optimization. b. Execution Efficiency with Correct by Construction Approach. c. Quality (Zero re-work) due to quality misses in intermediate milestone. d. Zero Post Silicon Bugs in Signoff e. Created A Captive teams from ground zero to operational excellence. Technical Expertise : (07nm,10nm,14nm,28nm,40nm,65nm implementation) Leading an Implementation team for RTL to SIGNOFF Flow. Seasoned in SOC Planning & Architectural requirements leading Execution plan via milestones. Expert in Driving Clock Strategy for SOC & Budget Techniques. Expert in Driving Power Requirements and strategy for SOC/SS. Expert in SoC Signoff Static Timing Analysis, Clock Management, DFX Concept & Mitigation Plan Formulating STA Strategies and Risk Management. Good Cross-functional Coordination and Mentoring. Managed SoC integration, Subsystem developement Managed Silicon Vadilation support. Had hands on IP and SOC verification, Emulation platform using Axis n specman. Extensively worked on high definition Set Top Box . 28+ APSOC Tapped out with Good Success record. Intel -
Deepak Garg currently works in the
Intel -
Deepak Garg specializes in
A Blend of StrongTechnical Competencies with Good Business Sense (MBA in International business from IIFT Delhi) and understanding of the Semiconductor Industry (BTech from NIT Warangal) with 22+ Years of Experience of Full ASIC Cycle. Having & Nurturing Portfolio of Constraints & Power Team & Signoff STA as proven Leaders. Good FE/DV fundamentals help me to drive BU with Correct by Construction Approach aiming Zero defect (FTSS) silicon with Competitive PPA. Leading & Managing Design & Signoff with Developing with various check and Conceptualizing Strategy for a. PPA optimization. b. Execution Efficiency with Correct by Construction Approach. c. Quality (Zero re-work) due to quality misses in intermediate milestone. d. Zero Post Silicon Bugs in Signoff e. Created A Captive teams from ground zero to operational excellence. Technical Expertise : (07nm,10nm,14nm,28nm,40nm,65nm implementation) Leading an Implementation team for RTL to SIGNOFF Flow. Seasoned in SOC Planning & Architectural requirements leading Execution plan via milestones. Expert in Driving Clock Strategy for SOC & Budget Techniques. Expert in Driving Power Requirements and strategy for SOC/SS. Expert in SoC Signoff Static Timing Analysis, Clock Management, DFX Concept & Mitigation Plan Formulating STA Strategies and Risk Management. Good Cross-functional Coordination and Mentoring. Managed SoC integration, Subsystem developement Managed Silicon Vadilation support. Had hands on IP and SOC verification, Emulation platform using Axis n specman. Extensively worked on high definition Set Top Box . 28+ APSOC Tapped out with Good Success record. -
Deepak Garg speaks the following languages:
No languages available. -
Deepak Garg has prior experience in the following industries:
Qualcomm , St Microelectronics , Wipro Technologies , Lecturer Adhoc Faculty Of Nit Jaipur And Gyan Vihar University -
Deepak Garg has the following professional experience:
Intel , Qualcomm , St Microelectronics , Wipro Technologies , Lecturer Adhoc Faculty Of Nit Jaipur And Gyan Vihar University , Intel . -
You can view Deepak Garg’s
LinkedIn profile at LinkedIn URL. -
Deepak Garg’s work email addresses are
[email protected] . -
Deepak Garg works at
Intel
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