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Deepak Jagannath

CORE COMPETENCIES @ Good Knowledge of ASIC flow (RTL to GDSII). @ In-depth understanding of RTL design (Verilog), Verification, Static Timing Analysis,... | San Jose, California, United States

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Deepak Jagannath’s Emails [email protected]

Deepak Jagannath’s Phone Numbers No phone number available.

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Deepak Jagannath’s Location San Jose, California, United States

Deepak Jagannath’s Expertise CORE COMPETENCIES @ Good Knowledge of ASIC flow (RTL to GDSII). @ In-depth understanding of RTL design (Verilog), Verification, Static Timing Analysis, Floorplan, Placement, CTS, Routing, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. @ An understanding of the Basic working of CMOS logic @ Have had exposure to industry std. tools like SOC Encounter, NanoRoute, Encounter Timing System, Star-RCXT, PT, PT-SI, Hercules, VirtuosoXL, Caliber @ Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming PERL, TCL, Awk, Sed, Verilog

Deepak Jagannath’s Current Industry Cadence Design Systems

Deepak Jagannath’s Prior Industry
Kawasaki Microelectronics | Megachips | Cadence Design Systems

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Work Experience

Cadence Design Systems

Engineer

Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Cadence Design Systems

Lead Design Engineer

Sat Nov 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Megachips

Sr Design Engineer

Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Kawasaki Microelectronics

Sr design engineer

Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

Deepak Jagannath Email Addresses

[email protected] Email

Deepak Jagannath Phone Number

No phone number available. Phone number

FAQ About Deepak Jagannath

Deepak Jagannath is located at
San Jose, California, United States

Deepak Jagannath is a
CORE COMPETENCIES @ Good Knowledge of ASIC flow (RTL to GDSII). @ In-depth understanding of RTL design (Verilog), Verification, Static Timing Analysis, Floorplan, Placement, CTS, Routing, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. @ An understanding of the Basic working of CMOS logic @ Have had exposure to industry std. tools like SOC Encounter, NanoRoute, Encounter Timing System, Star-RCXT, PT, PT-SI, Hercules, VirtuosoXL, Caliber @ Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming PERL, TCL, Awk, Sed, Verilog Cadence Design Systems

Deepak Jagannath currently works in the
Cadence Design Systems

Deepak Jagannath specializes in
CORE COMPETENCIES @ Good Knowledge of ASIC flow (RTL to GDSII). @ In-depth understanding of RTL design (Verilog), Verification, Static Timing Analysis, Floorplan, Placement, CTS, Routing, DFM, DRC, LVS, Parasitic Extraction, Schematic, Layout and Spice Simulation. @ An understanding of the Basic working of CMOS logic @ Have had exposure to industry std. tools like SOC Encounter, NanoRoute, Encounter Timing System, Star-RCXT, PT, PT-SI, Hercules, VirtuosoXL, Caliber @ Working knowledge of Unix/Linux, Sun-Solaris, VI editor and Programming PERL, TCL, Awk, Sed, Verilog