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Dev Desai

I firmly believe that I could be a proficient Digital Design & Verification Engineer with my research... | San Francisco, San Francisco, United States

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Dev Desai’s Location San Francisco, San Francisco, United States

Dev Desai’s Expertise I firmly believe that I could be a proficient Digital Design & Verification Engineer with my research project work experience. Motivated to work with experienced design engineer team. I have speciallized knowledge in following domain: 1) Computer Microarchitecture Design. (Experience: 2 Years) - Implemented 5 Stage Nios II Processor. - Implemented Basic Memory Controlller. 2) UVM based Verification of various DUTs. (Experience: 1Year) - Implemented UVM Testbench to verify different functionality of FIFO. - Implemented UVM Testbench to verify different functionality UART block of Atmel 8271 Microcontroller - Implemented UVM Testbench to verify different functionality AXI Bridge. 3) Hardware Design Using Verilog. (Experience: 2 Years) - Designing of double precision Floating point adder and multiplier with pipelining. - Designing & Optimizing of different 64 bit addrer (Ripple Carry Addder, Carry look ahead adder). - Designing of Parametrized FIFO. - Designing of different small Intlectual Properties. 4) Hardware Design Using System Verilog. (Experience: 1.5 Years) - Design of CRC block according to MKW2xD Microcontroller Family Specification. - Design of “Network on chip” & “Bus Master” - Design of “bidding Arbiter” with last won lowest priority. 5) Verification using System Verilog. (Experience: 1.5 Years) - Implemented System Verilog based testbench to verify Arithmatic & Logical Unit (ALU). 6) Test Automation using Python. (Experience: 1 Year) - Implemeted Python Script to Automate the UVM testbench Environment. 7) Design Automation using Perl. (Experience: 1 Year) - Implemented Perl Script to change verilog code of Multiplexer according to requirment. 8) FPGA Design. (Experience: 2 Years) - Design & Implementation of FIR Filter using MAC Unit 9) Embedded Design. (Experience: 5 Years) - Design & Development of Control Unit for CNC Machine Tool using Arduino Microcontroller.

Dev Desai’s Current Industry QuickLogic

Dev Desai’s Prior Industry
M/s Matrix Comsec Pvt. Ltd. | QuickLogic

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Work Experience

QuickLogic

Application Engineer Intern

Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

M/s Matrix Comsec Pvt. Ltd.

Summer Trainee

Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

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Dev Desai Email Addresses

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FAQ About Dev Desai

Dev Desai is located at
San Francisco, San Francisco, United States

Dev Desai is a
I firmly believe that I could be a proficient Digital Design & Verification Engineer with my research project work experience. Motivated to work with experienced design engineer team. I have speciallized knowledge in following domain: 1) Computer Microarchitecture Design. (Experience: 2 Years) - Implemented 5 Stage Nios II Processor. - Implemented Basic Memory Controlller. 2) UVM based Verification of various DUTs. (Experience: 1Year) - Implemented UVM Testbench to verify different functionality of FIFO. - Implemented UVM Testbench to verify different functionality UART block of Atmel 8271 Microcontroller - Implemented UVM Testbench to verify different functionality AXI Bridge. 3) Hardware Design Using Verilog. (Experience: 2 Years) - Designing of double precision Floating point adder and multiplier with pipelining. - Designing & Optimizing of different 64 bit addrer (Ripple Carry Addder, Carry look ahead adder). - Designing of Parametrized FIFO. - Designing of different small Intlectual Properties. 4) Hardware Design Using System Verilog. (Experience: 1.5 Years) - Design of CRC block according to MKW2xD Microcontroller Family Specification. - Design of “Network on chip” & “Bus Master” - Design of “bidding Arbiter” with last won lowest priority. 5) Verification using System Verilog. (Experience: 1.5 Years) - Implemented System Verilog based testbench to verify Arithmatic & Logical Unit (ALU). 6) Test Automation using Python. (Experience: 1 Year) - Implemeted Python Script to Automate the UVM testbench Environment. 7) Design Automation using Perl. (Experience: 1 Year) - Implemented Perl Script to change verilog code of Multiplexer according to requirment. 8) FPGA Design. (Experience: 2 Years) - Design & Implementation of FIR Filter using MAC Unit 9) Embedded Design. (Experience: 5 Years) - Design & Development of Control Unit for CNC Machine Tool using Arduino Microcontroller. QuickLogic

Dev Desai currently works in the
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Dev Desai specializes in
I firmly believe that I could be a proficient Digital Design & Verification Engineer with my research project work experience. Motivated to work with experienced design engineer team. I have speciallized knowledge in following domain: 1) Computer Microarchitecture Design. (Experience: 2 Years) - Implemented 5 Stage Nios II Processor. - Implemented Basic Memory Controlller. 2) UVM based Verification of various DUTs. (Experience: 1Year) - Implemented UVM Testbench to verify different functionality of FIFO. - Implemented UVM Testbench to verify different functionality UART block of Atmel 8271 Microcontroller - Implemented UVM Testbench to verify different functionality AXI Bridge. 3) Hardware Design Using Verilog. (Experience: 2 Years) - Designing of double precision Floating point adder and multiplier with pipelining. - Designing & Optimizing of different 64 bit addrer (Ripple Carry Addder, Carry look ahead adder). - Designing of Parametrized FIFO. - Designing of different small Intlectual Properties. 4) Hardware Design Using System Verilog. (Experience: 1.5 Years) - Design of CRC block according to MKW2xD Microcontroller Family Specification. - Design of “Network on chip” & “Bus Master” - Design of “bidding Arbiter” with last won lowest priority. 5) Verification using System Verilog. (Experience: 1.5 Years) - Implemented System Verilog based testbench to verify Arithmatic & Logical Unit (ALU). 6) Test Automation using Python. (Experience: 1 Year) - Implemeted Python Script to Automate the UVM testbench Environment. 7) Design Automation using Perl. (Experience: 1 Year) - Implemented Perl Script to change verilog code of Multiplexer according to requirment. 8) FPGA Design. (Experience: 2 Years) - Design & Implementation of FIR Filter using MAC Unit 9) Embedded Design. (Experience: 5 Years) - Design & Development of Control Unit for CNC Machine Tool using Arduino Microcontroller.