
Duncan Mackay
Experienced semiconductor design professional with a track record of successfully supporting and advancing leading edge methodologies for ASIC... | Portland, Oregon, United States
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Duncan Mackay’s Emails [email protected]
Duncan Mackay’s Phone Numbers No phone number available.
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Duncan Mackay’s Location Portland, Oregon, United States
Duncan Mackay’s Expertise Experienced semiconductor design professional with a track record of successfully supporting and advancing leading edge methodologies for ASIC and FPGA designs at multiple successful startups and in large complex organizations. Throughout my 20+ year career in IC/FPGA design and EDA application support, I have worked with leading edge customers to successfully proliferate the adoption of new methodologies, tools and technologies: starting with Design Compiler version 1.0.c I have been the lead AE for Behavioral Compiler (HLS), Power Compiler, PrimeTime, SLEC, PowerPro and Vivado HLS (the synthesis engine for Vitis ). As a top contributor, strong team member and team manager, my roles have included product specification and development, all aspects of customer support from pre-sales consultations through post-sales in-depth support, strategic partnerships, developing methodologies, creating complete documentation sets on different media, developing training, and leading global teams.
Duncan Mackay’s Current Industry Intel
Duncan
Mackay’s Prior Industry
Gould Electronics
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Sharp Electronics
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Synopsys
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Adaptive Silicon
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Leopard Logic
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Calypto Design Systems
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Autoesl
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Xilinx
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None
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Silexica
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Intel
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Work Experience

Intel
High Level Design Product Marketing Manager
Sat Jan 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Product Management Manager
Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Dec 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Silexica
FAE Lead
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
None
A Year Off
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Manager HLS SW Applications
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Sr. Staff Product Applications Engineer
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Autoesl
Principal Corprate Applications Engineer
Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Calypto Design Systems
Senior Member of Consulting Staff
Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Leopard Logic
Senior Applications Consultant
Fri Feb 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Adaptive Silicon
Technical Marketing Engineer
Thu Feb 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Staff Corporate Applications Engineer
Tue Oct 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
Sharp Electronics
ASIC Design Consultant
Wed May 01 1991 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)
Gould Electronics
ASIC Design Engineer
Fri Jul 01 1988 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 1991 00:00:00 GMT+0000 (Coordinated Universal Time)