
Giuseppe Curello
Strong hands on experience in Silicon Technology Development of most advanced Intel CMOS Logic nodes (90 to 14nm)...
Munich, Bavaria, Germany
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Giuseppe Curello’s Emails [email protected]
Giuseppe Curello’s Phone Numbers No phone number available.
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Giuseppe Curello’s Location Munich, Bavaria, Germany
Giuseppe Curello’s Expertise Strong hands on experience in Silicon Technology Development of most advanced Intel CMOS Logic nodes (90 to 14nm) as well as RF/mmW Device, ESD and Analog Circuit Design enablement for Intel Mobile Products in leading edge Foundry technologies. Excellent communication and versatility skills (in Research, Development and Production enviroments) spanning from process engineering, process integration, device performance, modeling, test and analog circuit design. Open and direct, successfull in challenging and time sensitive projects both as key team contributor and as project leader. International living and working experience (USA / Germany / UK), self motivated, initiative taker and committed. Holding both USA and ITA passport.
Giuseppe Curello’s Current Industry Apple
Giuseppe
Curello’s Prior Industry
Italian Army
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Siemens Microelectronics
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Infineon Technologies Dresden
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Intel
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Apple
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Work Experience

Apple
Cellular RF & Wireless Senior Silicon Technologist
Fri Sep 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Apple
Cellular Technologist
Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
RF / Analog Design Enablement Engineer
Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Analog and Mix Signal Design Engineer for ESD - Wireless Platform R&D
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Member of Technical Staff - Device Engineer - Intel Logic Technology Development
Thu Sep 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Sr. Device Engineer / Member of Technical Staff - Intel Logic Technology Development
Tue May 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies Dresden
Device/Integration Engineer
Sun Nov 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
Siemens Microelectronics
Implant Process Engineer (while completing PhD)
Thu Aug 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Italian Army
Lieutenant
Wed Apr 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)