
Greg Mann
Digital IC Design Engineer with expertise in Design and Verification using Verilog HDL, Design for Testability (DFT), Logic... | 4818 Avondale Circle, Colorado Springs, United States
*50 free lookup(s) per month.
No credit card required.
Greg Mann’s Emails [email protected]
Greg Mann’s Phone Numbers No phone number available.
Social Media
Greg Mann’s Location 4818 Avondale Circle, Colorado Springs, United States
Greg Mann’s Expertise Digital IC Design Engineer with expertise in Design and Verification using Verilog HDL, Design for Testability (DFT), Logic Synthesis using Synopsys Design Compiler, and FPGA-based design using Xilinx ISE. Supporting competencies include Design Reuse/Reusability, Static Timing Analysis, Cadence Spectre, Ocean (Skill) Programming, Tcl/Tk Programming, and Perl Programming.
Greg Mann’s Current Industry Broadcom
Greg
Mann’s Prior Industry
Honeywell
|
Minc
|
Ford Microelectronics
|
Sanmina Sci
|
Simtek
|
Organicid
|
Cypress Semiconductor
|
Astek
|
Agilent Technologies
|
Jdsu
|
Lsi
|
Avago Technologies
|
Broadcom
Not the Greg Mann you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Broadcom
IC Design Engineer
Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Avago Technologies
IC Design Engineer
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi
Staff IC Design Engineer
Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Jdsu
Sr HW Development Engineer
Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Agilent Technologies
R&D Electrical Engineer
Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Astek
Senior Digital Design Engineer
Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Cypress Semiconductor
Digital IC Design Contractor
Mon Dec 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Organicid
IC Design Contractor
Wed Oct 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Simtek
IC Design Engineer
Tue Jun 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Sanmina Sci
Quality Engineer
Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Ford Microelectronics
IC Design Engineer
Sat Sep 01 1990 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Honeywell
Engineering Intern
Sun Nov 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time)
Minc
Engineering Intern
Tue Sep 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time)
Honeywell
Engineering Intern
Sat Mar 01 1986 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Oct 01 1986 00:00:00 GMT+0000 (Coordinated Universal Time)