
Harminder Bagga
HW/SW Co-Emulation and Emulation Activities, SystemC/System-Verilog based verification at IP and SOC level, Worked on Emulation technologies... | Fremont, California, United States
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Harminder Bagga’s Emails ha****@sa****.com
Harminder Bagga’s Phone Numbers 1800425****
Social Media
Harminder Bagga’s Location Fremont, California, United States
Harminder Bagga’s Expertise HW/SW Co-Emulation and Emulation Activities, SystemC/System-Verilog based verification at IP and SOC level, Worked on Emulation technologies like -Xtreme, Palladium, Pxp by Cadence and Veloce by Mentor Graphics, and Pre-Silicon Validation using standard ISolve solution by Mentor Graphics and Pxp. Specialties: I am involoved in working at IP level as well as SOC level Emulation and Co-Emulation activities, SystemC based platform verification and automation, Transactional Level Modelling, Worked on SceMi 2.1 level platforms, Architectural analysis, Verification using C/Verilog/SV
Harminder Bagga’s Current Industry Samsung Austin Semiconductor
Harminder
Bagga’s Prior Industry
Wipro Technologies
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St Microelectronics
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Stmicroelectronics
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Mentor Graphics
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Samsung Electronics
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Samsung Sarc
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Samsung Austin Semiconductor
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Work Experience

Samsung Austin Semiconductor
Principal Engineer
Mon May 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung Sarc
Senior Staff Engineer
Fri Mar 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung Electronics
Staff Engineer
Mon May 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Mentor Graphics
Senior Emulation Application Engineer
Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Staff Engineer
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
St Microelectronics
Technical Leader
Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Wipro Technologies
Senior Design Engineer
Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)