Hemil Patel
• MSEE with 20 years of experience in ASIC Implementation and Applications Engineering. • ASIC Implementation experience includes RTL... | Santa Clara, California, United States
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Hemil Patel’s Emails hp****@br****.com
Hemil Patel’s Phone Numbers No phone number available.
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Hemil Patel’s Location Santa Clara, California, United States
Hemil Patel’s Expertise • MSEE with 20 years of experience in ASIC Implementation and Applications Engineering. • ASIC Implementation experience includes RTL to GDS and CAD methodology/flow development using Synopsys, Atoptech, Apache, Cadence and Mentor Graphics tools. Hands on experience in Synthesis, Floorplanning, Place & Route, CTS, Timing Closure, Formal Verification, Signal Integrity & EM Analysis, Power & Yield (DFM/DFY) and Physical Verification. • Applications experience includes providing Presales, Proactive and Reactive support for IC Compiler, Physical Compiler, Design Compiler, DFT Compiler, Power Compiler, PrimeTime and PrimeTime-SI. Specialties: ASIC Design, Timing Closure, Place & Route, Methodology & Flow Development, EDA Applications
Hemil Patel’s Current Industry Broadcom
Hemil
Patel’s Prior Industry
Lsi Logic
|
Synopsys
|
Marvell Semiconductor
|
Broadcom
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Work Experience
Broadcom
Sr. Principal Physical Design Engineer
Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Marvell Semiconductor
Sr. Physical Design Manager
Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Synopsys
Staff Applications Consultant
Fri Jun 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Lsi Logic
ASIC Customer Engineer
Sat Aug 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jun 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Hemil Patel Email Addresses
FAQ About Hemil Patel
-
Hemil Patel is located at
Santa Clara, California, United States -
Hemil Patel is a
• MSEE with 20 years of experience in ASIC Implementation and Applications Engineering. • ASIC Implementation experience includes RTL to GDS and CAD methodology/flow development using Synopsys, Atoptech, Apache, Cadence and Mentor Graphics tools. Hands on experience in Synthesis, Floorplanning, Place & Route, CTS, Timing Closure, Formal Verification, Signal Integrity & EM Analysis, Power & Yield (DFM/DFY) and Physical Verification. • Applications experience includes providing Presales, Proactive and Reactive support for IC Compiler, Physical Compiler, Design Compiler, DFT Compiler, Power Compiler, PrimeTime and PrimeTime-SI. Specialties: ASIC Design, Timing Closure, Place & Route, Methodology & Flow Development, EDA Applications Broadcom -
Hemil Patel currently works in the
Broadcom -
Hemil Patel specializes in
• MSEE with 20 years of experience in ASIC Implementation and Applications Engineering. • ASIC Implementation experience includes RTL to GDS and CAD methodology/flow development using Synopsys, Atoptech, Apache, Cadence and Mentor Graphics tools. Hands on experience in Synthesis, Floorplanning, Place & Route, CTS, Timing Closure, Formal Verification, Signal Integrity & EM Analysis, Power & Yield (DFM/DFY) and Physical Verification. • Applications experience includes providing Presales, Proactive and Reactive support for IC Compiler, Physical Compiler, Design Compiler, DFT Compiler, Power Compiler, PrimeTime and PrimeTime-SI. Specialties: ASIC Design, Timing Closure, Place & Route, Methodology & Flow Development, EDA Applications -
Hemil Patel speaks the following languages:
No languages available. -
Hemil Patel has prior experience in the following industries:
Marvell Semiconductor , Synopsys , Lsi Logic -
Hemil Patel has the following professional experience:
Broadcom , Marvell Semiconductor , Synopsys , Lsi Logic . -
You can view Hemil Patel’s
LinkedIn profile at LinkedIn URL. -
Hemil Patel’s work email addresses are
[email protected] . -
Hemil Patel works at
Broadcom
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