Hossein Sereshki

Hossein Sereshki

I am a Senior ASIC Design Verification Engineer with over 20 years of experience in ASIC and FPGA,... | San Jose, California, United States

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Work Experience

Accenture

Silicon SOC Design Verification - Accenture Corp

Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Advantest

Verification Architect

Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Encore Semi

Senior Verification Engineer

Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Ngd Systems

Senior Verification Engineer (Technical Link)

Fri Sep 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Associate Product Architect (UST Global)

Sat Apr 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Qualcomm

Senior ASIC Verification Engineer

Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Micron Technology

ASIC Verification Engineer

Tue Apr 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Amd

Senior Consultant

Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Full Chip Verification Contractor

Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)

Lattice Semiconductor

Staff Software Engineer

Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Sep 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)

Altera

Simulation Software Manager

Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Altera

EDA Software Supervisor

Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)

Altera

Technical Marketing, Program Manager

Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time)

Lsi Logic

Application Engineer

Sun Jan 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1992 00:00:00 GMT+0000 (Coordinated Universal Time)

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