
Jaime Bulnes
Jaime Bulnes is in-house counsel with Intel Corporation. Mr. Bulnes was previously an Associate in the Austin... | 7425 Magenta Lane, Austin, United States
*50 free lookup(s) per month.
No credit card required.
Jaime Bulnes’s Emails bu****@fr****.com
Jaime Bulnes’s Phone Numbers No phone number available.
Social Media
Jaime Bulnes’s Location 7425 Magenta Lane, Austin, United States
Jaime Bulnes’s Expertise Jaime Bulnes is in-house counsel with Intel Corporation. Mr. Bulnes was previously an Associate in the Austin office of Fish & Richardson. His practice emphasized patent litigation and patent prosecution (2007-2012). Mr. Bulnes was also a Summer Associate with the firm (2006). He is also a former Legal Intern in the Patent and Licensing Group for Intel Corporation (2005-2006), and a Patent Application Consultant for Silicon Quest, Inc. (2004). Mr. Bulnes has technical experience as a former Device Engineer for Sony Semiconductor of America (2000-2003), as well as a Test Engineer in the BiCMOS Division of Sony Semiconductor (1998-2000). Specialties: Computer Architecture, Memory Systems, Digital Circuitry, Semiconductor Processing, Embedded Applications, Power Systems
Jaime Bulnes’s Current Industry Intel
Jaime
Bulnes’s Prior Industry
Sony Semiconductor
|
Intel
|
Fish And Richardson
Not the Jaime Bulnes you were looking for?
Find accurate emails & phone numbers for over 700M professionals.
Work Experience

Intel
Attorney
Sat Sep 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Fish And Richardson
Attorney
Sat Sep 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Legal Intern, Patent and Licensing Group
Sun May 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Sony Semiconductor
Device Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Sony Semiconductor
BiCMOS Test Engineer
Thu Jan 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)