Jeff Riley

FAQ About Jeff Riley

• What is Jeff Riley's address?

  Jeff Riley is located at
  The Randstad, The Randstad, Netherlands

• What is Jeff Riley's job title?

  Jeff Riley is a
  ASIC/FPGA Design Engineer with a proven ability to work and thrive both independently and in a team environment, prioritizing multiple projects and meeting deadlines. Functions well in a team environment communicating effectively with all levels of an organization. Eleven years of ASIC/FPGA design flow experience with demonstrated technical expertise in the following areas: * Data compression and encryption * Verilog and VHDL for RTL or behavioral modeling * Logic synthesis using Synopsys Design Compiler, Synplicity Synplify Pro, and Xilinx ISE/XST * Studied Magma synthesis and layout for RTL to GDSII flow. * RTL/Gate level simulation using Synopsys VCS, debug using Novas Verdi/Debussy * DFT methodology * ATPG using Synopsys TetraMAX * JTAG insertion using Synopsys BSD Compiler * Formal Verification with Logic Equivalency checking using Verplex LEC * Tcl/Tk scripting language * C for embedded applications and utility applications Specialties: RTL design/implementation, synthesis, and verification. Broadcom

• What industry does Jeff Riley currently work in?

  Jeff Riley currently works in the
  Broadcom

• What is Jeff Riley's area of expertise?

  Jeff Riley specializes in
  ASIC/FPGA Design Engineer with a proven ability to work and thrive both independently and in a team environment, prioritizing multiple projects and meeting deadlines. Functions well in a team environment communicating effectively with all levels of an organization. Eleven years of ASIC/FPGA design flow experience with demonstrated technical expertise in the following areas: * Data compression and encryption * Verilog and VHDL for RTL or behavioral modeling * Logic synthesis using Synopsys Design Compiler, Synplicity Synplify Pro, and Xilinx ISE/XST * Studied Magma synthesis and layout for RTL to GDSII flow. * RTL/Gate level simulation using Synopsys VCS, debug using Novas Verdi/Debussy * DFT methodology * ATPG using Synopsys TetraMAX * JTAG insertion using Synopsys BSD Compiler * Formal Verification with Logic Equivalency checking using Verplex LEC * Tcl/Tk scripting language * C for embedded applications and utility applications Specialties: RTL design/implementation, synthesis, and verification.

• Which languages does Jeff Riley speak? 

  Jeff Riley speaks the following languages:
  No languages available.

• Which industries has Jeff Riley previously worked in?   

  Jeff Riley has prior experience in the following industries:
  Marvell Semiconductor , Quantum , Conexant , Mindspeed , T2design

• What is Jeff Riley’s work experience?  

  Jeff Riley has the following professional experience:
  Broadcom , Marvell Semiconductor , Quantum , Conexant , Mindspeed , T2design .

• How can I find Jeff Riley on LinkedIn?  

  You can view Jeff Riley’s
  LinkedIn profile at LinkedIn URL.

• What are Jeff Riley’s work email addresses?  

  Jeff Riley’s work email addresses are
  [email protected] .

• What company does Jeff Riley work for?  

  Jeff Riley works at
  Broadcom