Joe Logan
Extensive experience in logic design of custom chips and ASICs for applications including high performance bus interconnects (crossbar,... | Apex, North Carolina, United States
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Joe Logan’s Emails jl****@qu****.com
Joe Logan’s Phone Numbers No phone number available.
Social Media
Joe Logan’s Location Apex, North Carolina, United States
Joe Logan’s Expertise Extensive experience in logic design of custom chips and ASICs for applications including high performance bus interconnects (crossbar, ring, mesh), high performance CPU pipelines (load/store, fixed point, L3 snoop), networking products (packet routing/switching, network processors, media access control), and high speed serial links (6 to 28 Gbps). Experienced in all phases of the front end chip design process including product definition, micro-architecture, RTL coding, design verification, synthesis, timing analysis, asynchronous interface analysis, and design for test. Skilled in design of fundamental building blocks implementing features such as async FIFOs, Virtual Channel queuing, packet routing/switching, bus protocols, arbitration, flow control, and quality of service. Strong technical writing skills (author of multiple customer databooks and bus specifications).
Joe Logan’s Current Industry Intel
Joe
Logan’s Prior Industry
Ibm
|
Qualcomm
|
Barefoot Networks
|
Intel
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Work Experience
Intel
Hardware Engineer at Intel
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Barefoot Networks
Hardware Engineer at Barefoot Networks
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Senior Staff Engineer
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Senior Engineer
Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Senior Engineer
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Senior Engineer
Wed Dec 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Senior Engineer
Fri Nov 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Advisory Engineer
Thu Apr 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Oct 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Staff Engineer
Sat Apr 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Senior Associate Engineer
Sun Jan 01 1984 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 1989 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Joe Logan Email Addresses
FAQ About Joe Logan
-
Joe Logan is located at
Apex, North Carolina, United States -
Joe Logan is a
Extensive experience in logic design of custom chips and ASICs for applications including high performance bus interconnects (crossbar, ring, mesh), high performance CPU pipelines (load/store, fixed point, L3 snoop), networking products (packet routing/switching, network processors, media access control), and high speed serial links (6 to 28 Gbps). Experienced in all phases of the front end chip design process including product definition, micro-architecture, RTL coding, design verification, synthesis, timing analysis, asynchronous interface analysis, and design for test. Skilled in design of fundamental building blocks implementing features such as async FIFOs, Virtual Channel queuing, packet routing/switching, bus protocols, arbitration, flow control, and quality of service. Strong technical writing skills (author of multiple customer databooks and bus specifications). Intel -
Joe Logan currently works in the
Intel -
Joe Logan specializes in
Extensive experience in logic design of custom chips and ASICs for applications including high performance bus interconnects (crossbar, ring, mesh), high performance CPU pipelines (load/store, fixed point, L3 snoop), networking products (packet routing/switching, network processors, media access control), and high speed serial links (6 to 28 Gbps). Experienced in all phases of the front end chip design process including product definition, micro-architecture, RTL coding, design verification, synthesis, timing analysis, asynchronous interface analysis, and design for test. Skilled in design of fundamental building blocks implementing features such as async FIFOs, Virtual Channel queuing, packet routing/switching, bus protocols, arbitration, flow control, and quality of service. Strong technical writing skills (author of multiple customer databooks and bus specifications). -
Joe Logan speaks the following languages:
No languages available. -
Joe Logan has prior experience in the following industries:
Intel , Barefoot Networks , Qualcomm , Ibm , Ibm , Ibm , Ibm , Ibm , Ibm , Ibm -
Joe Logan has the following professional experience:
Intel , Barefoot Networks , Qualcomm , Ibm , Ibm , Ibm , Ibm , Ibm , Ibm , Ibm . -
You can view Joe Logan’s
LinkedIn profile at LinkedIn URL. -
Joe Logan’s work email addresses are
[email protected] . -
Joe Logan works at
Intel
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