Joe Maciel
SUMMARY OF QUALIFICATIONS Experienced in Hardware Engineering, R&D, Manufacturing, and Failure Analysis. Diverse knowledge in engineering and technical disciplines;... | San Francisco Bay Area, San Francisco Bay Area, United States
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Joe Maciel’s Emails jm****@ja****.com
Joe Maciel’s Phone Numbers No phone number available.
Social Media
Joe Maciel’s Location San Francisco Bay Area, San Francisco Bay Area, United States
Joe Maciel’s Expertise SUMMARY OF QUALIFICATIONS Experienced in Hardware Engineering, R&D, Manufacturing, and Failure Analysis. Diverse knowledge in engineering and technical disciplines; Electronics Engineering, Electro-Mechanical, Computer Aided Design, and PCB Design & Layout, and hands-on Technical Support & Service. CORE COMPETENCIES • Electronics: Analog/Digital Circuit Analysis, Testing, Debugging, Root Cause Analysis • Electro-Mechanical Fabrication: Prototyping, Test Hardware/Fixture, Mechanical Systems • Printed Circuit Board: Prototyping, Component Level Repair/Rework, High Reliability Soldering • Printed Circuit Design and Layout: Software — Mentor PADS Professional, AutoCAD
Joe Maciel’s Current Industry Nuro
Joe
Maciel’s Prior Industry
Seeq Technology
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Adaptec
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Xilinx
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Altera
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Microsoft Danger Subsidiary
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Maxim Integrated
|
Jawbone
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Apple
|
Nuro
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Work Experience
Nuro
ProtoFab & Test System Engineer
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Apple
Logistical Lab Manager
Mon Oct 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Apple
Tools & Automation Engineer
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Jawbone
Failure Analysis Test Engineer
Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Maxim Integrated
Application Engineering Aide - Contractor
Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Mar 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Microsoft Danger Subsidiary
Quality Assurance Engineer – Contractor
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Oct 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Manufacturing Engineer – Design Test Hardware, PCB Design & Layout
Mon Jun 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Electronics Technician
Mon Jan 01 1996 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Electronics Technician
Mon Aug 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time)
Adaptec
Electronics Technician
Fri Jan 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time)
Seeq Technology
Engineering Technician
Tue May 01 1984 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Joe Maciel Email Addresses
FAQ About Joe Maciel
-
Joe Maciel is located at
San Francisco Bay Area, San Francisco Bay Area, United States -
Joe Maciel is a
SUMMARY OF QUALIFICATIONS Experienced in Hardware Engineering, R&D, Manufacturing, and Failure Analysis. Diverse knowledge in engineering and technical disciplines; Electronics Engineering, Electro-Mechanical, Computer Aided Design, and PCB Design & Layout, and hands-on Technical Support & Service. CORE COMPETENCIES • Electronics: Analog/Digital Circuit Analysis, Testing, Debugging, Root Cause Analysis • Electro-Mechanical Fabrication: Prototyping, Test Hardware/Fixture, Mechanical Systems • Printed Circuit Board: Prototyping, Component Level Repair/Rework, High Reliability Soldering • Printed Circuit Design and Layout: Software — Mentor PADS Professional, AutoCAD Nuro -
Joe Maciel currently works in the
Nuro -
Joe Maciel specializes in
SUMMARY OF QUALIFICATIONS Experienced in Hardware Engineering, R&D, Manufacturing, and Failure Analysis. Diverse knowledge in engineering and technical disciplines; Electronics Engineering, Electro-Mechanical, Computer Aided Design, and PCB Design & Layout, and hands-on Technical Support & Service. CORE COMPETENCIES • Electronics: Analog/Digital Circuit Analysis, Testing, Debugging, Root Cause Analysis • Electro-Mechanical Fabrication: Prototyping, Test Hardware/Fixture, Mechanical Systems • Printed Circuit Board: Prototyping, Component Level Repair/Rework, High Reliability Soldering • Printed Circuit Design and Layout: Software — Mentor PADS Professional, AutoCAD -
Joe Maciel speaks the following languages:
No languages available. -
Joe Maciel has prior experience in the following industries:
Apple , Apple , Jawbone , Maxim Integrated , Microsoft Danger Subsidiary , Altera , Altera , Xilinx , Adaptec , Seeq Technology -
Joe Maciel has the following professional experience:
Nuro , Apple , Apple , Jawbone , Maxim Integrated , Microsoft Danger Subsidiary , Altera , Altera , Xilinx , Adaptec , Seeq Technology . -
You can view Joe Maciel’s
LinkedIn profile at LinkedIn URL. -
Joe Maciel’s work email addresses are
[email protected] . -
Joe Maciel works at
Nuro
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