
Johnny Chang
11+ years experience of device level and system level Failure Analysis included consumer and industry field. Workout with... | San Francisco Bay Area, San Francisco Bay Area, United States
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Johnny Chang’s Location San Francisco Bay Area, San Francisco Bay Area, United States
Johnny Chang’s Expertise 11+ years experience of device level and system level Failure Analysis included consumer and industry field. Workout with laboratory, use lab tools such as ATE, Oscilloscope, Curve tracer, ZAP master, ZAP gun, Build in chamber, Temperature forcing system, Liquid crystal, Emission scope, OBIRCH, Thermal scope, EDS, SEM, C-SEM, X-ray to discover the root causes on failure cases and problem solves with aviation, sailing, automobile and military related customer applications. 11+ years of reliability test experience for device level and system level such as ESD, Latch-Up, HTOL, LTOL, THB, and Hot-temp/Low-temp system functional confirmation. 11+ years experience to implement the System Level Test to solve the issues has been discovered by FA issues. Develop for exist/new products included hardware coordinate, test program analyzing and system setup, test procedure optimize, yield analysis and System Level Test production line engineering support. 11+ years experience workout with sub contractors in USA/TAIWAN to ensure the production quality. 2+ years experience Front line engineer to handle the PC related production line and re-work line in charge. 12+ years of specialized field of analog/digital Image, Video and Color inspection. 2+ years of 3D/2D CG production. Utility usage: Cadence OrCAD, Power PCB, Autodesk Fusion 360, 3D Go, Ulead video studio, Adobe Photoshop, Adobe Premiere, Major 3D/2D CG utility on SGI workstation, Microsoft office.
Johnny Chang’s Current Industry Google
Johnny
Chang’s Prior Industry
Taiwan Transtech
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Super Art
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Jaton
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Techwell
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Intersil
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At And T
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Intel
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Miltope
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Work Experience

Failure Analyst
Sat Oct 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Miltope
SF bayarea Service Representative
Thu Mar 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Engineering device manufacture
Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
At And T
Plant Engineer
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intersil
Sr. Product Engineer
Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Techwell
Product/FA Engineer
Thu Apr 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Jaton
Production Enineer, QC/Rework line supervisor
Sun Feb 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)
Super Art
VP of Production
Sun Jan 01 1995 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Mar 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)
Taiwan Transtech
Project manager
Thu Jan 01 1987 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time)