
Kapil Dholakiya
No headline available | San Jose, California, United States
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Kapil Dholakiya’s Emails ka****@mi****.com
Kapil Dholakiya’s Phone Numbers No phone number available.
Social Media
Kapil Dholakiya’s Location San Jose, California, United States
Kapil Dholakiya’s Expertise Lead Design Verification Engineer at Microsoft
Kapil Dholakiya’s Current Industry Microsoft
Kapil
Dholakiya’s Prior Industry
Enfochips
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Einfochips
|
Intel
|
Kioxia America Toshiba America Electronic Components
|
Nxp Marvell Semiconductor
|
Microsoft
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Work Experience

Microsoft
Design Verification Lead
Sat Aug 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Nxp Marvell Semiconductor
Design Verification Enginer Lead
Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Kioxia America Toshiba America Electronic Components
Sr.Design Verification Engineer
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jun 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engineer
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Enfochips
ASIC Engineer
Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
ASIC Verification Engineer
Thu Mar 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Nov 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)