
Kavoos Hedayati
Staff Hardware Designer designing High speed printed circuit boards. Highspeed ATE Final test and Characterization PCB design: Define... | 249 Christopher Drive, San Francisco, United States
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Kavoos Hedayati’s Location 249 Christopher Drive, San Francisco, United States
Kavoos Hedayati’s Expertise Staff Hardware Designer designing High speed printed circuit boards. Highspeed ATE Final test and Characterization PCB design: Define design guidelines based on customer requirements and release to Layout vendor, Review Schematic and Layout using Cadence Allegro and Schematic Capture before releasing to FAB Socket Design (BGA) Performing Signal Integrity simulation using Ansys HFSS/SIWAVE for critical highspeed signals and reviewing S-parameter plot insuring customer SI requirements Performing Power Integrity simulation using Ansys SIWAVE and Cadence Sigrity, Analyzing IR drop for DC analysis and Z-plot for AC analysis, optimizing decoupling cap placement and values based on customer power requirements Creating Mechanical models and running stress simulation using Solidworks insuring the testability of Xilinx Chip in our test environment Designing mechanical solutions for air flow under ATE test board to prevent moist buildup in temperature testing. This acted as supporting bar to prevent Board from sagging under test Proficiency using Scope and signal generator/analyzers to validate boards before releasing to customer and identify issues in the existing boards and fix them Study of the product roadmap, architecture and migration to insure the availability of required test hardware prior to product availability Cross group communication between IC packaging, Architecture and test engineering group to insure the testability of product and meeting customer needs Vendor qualification including test Socket, PCB Schematic, Layout and FAB vendors
Kavoos Hedayati’s Current Industry Rivian
Kavoos
Hedayati’s Prior Industry
Xilinx
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Amd
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Rivian
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Work Experience

Rivian
Staff Signal and Power Integrity Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Amd
Staff Hardware Design Engineer at AMD
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Staff Hardware Design Engineer
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Senior Hardware Design Engineer
Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Technical Marketing Engineer , Competitive Analyst
Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Application engineer
Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)