
Kumar Davinder
18+ years of extensive experience in RTL Design and Verification with main focus and expertise in pre-silicon validation... | Bengaluru, Karnataka, India
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Kumar Davinder’s Location Bengaluru, Karnataka, India
Kumar Davinder’s Expertise 18+ years of extensive experience in RTL Design and Verification with main focus and expertise in pre-silicon validation and DV architecture. Managed the soft IP RTL design and DV team with complete ownership of large IP portfolio in 5G domain. Successfully managed various wireless/wireline automotive and IoT projects, well versed with HW Design/verification methodologies. Expertise in chip development from RTL2GDS, lead to successful silicon proven tape-outs, hands-on experience on different phases of ASIC design cycles concept, frontend/backend design & verification, synthesis, equivalence, timing..etc Project management certification by Global Business Management Consultants US, managed couple of chip tape-outs with complete focus on technical quality & schedule commitment, where multi-site Geo,s teams getting involved.
Kumar Davinder’s Current Industry Intel
Kumar
Davinder’s Prior Industry
Tata Elxsi
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Infineon Technologies
|
Intel
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Work Experience

Intel
Sr. Engineering Manager Soc Design
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Engineering Manager Soc Design
Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Engineering Manager
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Nov 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Member Technical Staff - Mts
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Staff Engineer
Sun Feb 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Sr. Design Engineer - Complete Ownership From R2g Soc
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Tata Elxsi
Design Engineer
Wed Jan 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)