
Mahendran Chinnusamy
Experienced Senior FPGA Engineer with a demonstrated history of leading development and taking responsibility for the FPGA part... | Magna International, Jakob-Latscha-Str. 3, Germany
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Mahendran Chinnusamy’s Emails ma****@ma****.com
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Mahendran Chinnusamy’s Location Magna International, Jakob-Latscha-Str. 3, Germany
Mahendran Chinnusamy’s Expertise Experienced Senior FPGA Engineer with a demonstrated history of leading development and taking responsibility for the FPGA part of customer projects on SoCs, from requirement analysis to execution, with many years of experience with Embedded Systems, both on the system and FPGA deign level, and holding a Master's Degree in Electrical Engineering from Hochschule Darmstadt in Germany.
Mahendran Chinnusamy’s Current Industry Magna Electronic
Mahendran
Chinnusamy’s Prior Industry
Tata Telecom Avaya
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Infineon Technologies
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Hightronix
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Broadcast Microwave Services
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Magna Electronics
|
Magna Electronic
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Work Experience

Magna Electronic
Global Lead, FPGA Engineering (Interim)
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Magna Electronics
System Architect (Interim)
Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Magna Electronics
Senior FPGA Engineer
Thu Nov 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Broadcast Microwave Services
FPGA Engineer
Thu May 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Hightronix
FPGA Engineer
Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Master Thesis
Sun Oct 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Temporary Student Employee
Sat Apr 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Sep 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Infineon Technologies
Internship
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Tata Telecom Avaya
Software Engineer
Thu May 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)