Mark Debbage

Mark Debbage

No headline available | Santa Clara, Santa Clara, United States

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Work Experience

Intel

Senior Principal Engineer

Thu Mar 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Qlogic

Senior Principal Engineer

Sat Apr 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Pathscale

Principal Engineer

Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Apr 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)

Sun Microsystems

Senior Performance Engineer

Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Sep 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)

Superh

Senior Architect

Sat Sep 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Apr 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)

Stmicroelectronics

Senior Architect

Wed Sep 01 1993 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Sep 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Senior Principal Engineer

— Present

Skills

Languages

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