
Mayank Rege
Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Perl, C++, Universal... | Mumbai, Maharashtra, India
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Mayank Rege’s Emails ma****@so****.com
Mayank Rege’s Phone Numbers 1858651****
Social Media
Mayank Rege’s Location Mumbai, Maharashtra, India
Mayank Rege’s Expertise Experienced Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Perl, C++, Universal Verification Methodology (UVM), SystemVerilog, and Microprocessors. Strong engineering professional with a Master of Science focused in Computer Engineering from Syracuse University LC Smith College of Engineering.
Mayank Rege’s Current Industry Qualcomm
Mayank
Rege’s Prior Industry
Intel
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Tutors
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Indore Institute Of Science And Technology Indore Mp
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Achala Technologies
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Soft Machines
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Mirafra Technologies
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Arm
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Qualcomm
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Work Experience

Qualcomm
Staff Engineer/Manager
Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Staff Engineer
Fri May 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Aug 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Arm
Senior Engineer
Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Mirafra Technologies
Manager - Verification
Mon Jan 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Mirafra Technologies
Senior Verification Engineer
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Dec 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Soft Machines
Design Engineer
Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Achala Technologies
Soc Asic Ip Verification Engineer
Fri Feb 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Indore Institute Of Science And Technology Indore Mp
Assistant Professor
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Tutors
Tutoring
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Dec 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Component Design Engg
Sat Nov 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)