
Meha Kainth
- Extensive experience in FPGA design and SOC Emulation. Interested in Logic design/verification for FPGA/ASICs. - Verilog/ VHDL... | San Jose, California, United States
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Meha Kainth’s Emails me****@in****.com
Meha Kainth’s Phone Numbers No phone number available.
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Meha Kainth’s Location San Jose, California, United States
Meha Kainth’s Expertise - Extensive experience in FPGA design and SOC Emulation. Interested in Logic design/verification for FPGA/ASICs. - Verilog/ VHDL RTL, C/ C++, System Verilog, scripting languages: Perl, TCL, - RTL design and simulation, logic synthesis and timing analysis, hardware bring up, lab debug tools - Synopsys ‘Zebu’ emulator, Verdi, VCS, System Verilog Assertions, Synopsys DC, MATLAB -GIT, Perforce, bash, shell scripting, Repositories
Meha Kainth’s Current Industry Intel
Meha
Kainth’s Prior Industry
Defence Research And Development Organisation
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Giant Metrewave Radio Telescope Tata Institute Of Fundamental Research
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Nsn Nokia Solutions And Networks
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Jtpl
|
Reconfigurable Computing Group University Of Massachusetts Amherst
|
The Mathworks
|
Altera
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Intel
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Work Experience

Intel
Emulation Engineer
Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
SOC Design Engineer (FPGA)
Fri Jan 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Altera
Design Engineer II
Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Reconfigurable Computing Group University Of Massachusetts Amherst
Research Assistant
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
The Mathworks
FPGA Targets Intern
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Dec 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Reconfigurable Computing Group University Of Massachusetts Amherst
Research Assistant
Wed Jan 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Jtpl
Hardware Engineer
Fri Apr 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Nsn Nokia Solutions And Networks
Core Planning Engineer
Mon Feb 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Mar 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Giant Metrewave Radio Telescope Tata Institute Of Fundamental Research
Student Trainee
Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Defence Research And Development Organisation
Intern
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time)