
Michael Brannigan-Pmp
Physical Design, Timing Verification, Memory Design, and Engineering project management. IP development using multiple processes (Samsung, TSMC) to... | 9512 Indina Hills Drive, Austin, United States
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Michael Brannigan-Pmp’s Emails mi****@in****.com
Michael Brannigan-Pmp’s Phone Numbers No phone number available.
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Michael Brannigan-Pmp’s Location 9512 Indina Hills Drive, Austin, United States
Michael Brannigan-Pmp’s Expertise Physical Design, Timing Verification, Memory Design, and Engineering project management. IP development using multiple processes (Samsung, TSMC) to 3 nm. Physical design background includes all phases of ASIC / SOC design - synthesis, timing closure, and place and route using tool suites from Synopsys, and Cadence Design Systems. Specialties: * Physical Design, ASIC Design, Mixed-Signal Design, Timing, Transistor-level Design * Development Flows using Cadence, and Synopsys tool suites * Technical Project Management, Project Planning, Cross-functional Team Leadership * Synthesis, Circuit Simulation, and Verification * HSPICE, Spectre, Finesim, SPICE * RTL, Timing, IR Drop Analysis * Signal Integrity, Low Power * Verilog, System Verilog, RTL, compiler * Tcl, Perl, Java / Oracle
Michael Brannigan-Pmp’s Current Industry Infinisim
Michael
Brannigan-Pmp’s Prior Industry
Stmicroelectronics
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Broadcom
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Vitesse Semiconductor
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Magma Design Automation
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Freescale Semiconductor
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Texas Insruments
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Ibm
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Qualcomm
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Intel
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Nxp Semiconductors
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Synapse Design
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Infinisim
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Work Experience

Infinisim
Application / Design Engineer
Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
Design Enablement Engineer
Sun May 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Memory and IP Design Engineer
Thu Jul 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Synapse Design
Physical Design Engineer
Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jun 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Physical Design Engineer
Sat Feb 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Nxp Semiconductors
CAD Engineer - Timing Verification / Correlation Consultant
Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Circuit Design | IP Design | Timing Engineer Consultant
Wed Nov 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jul 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Foundary Collateral Development Engineer Consultant
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jul 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Timing / Integration Engineer Consultant
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Ibm
Analog and Mixed-Signal Design / Integration Engineer Consultant
Sat Jan 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Insruments
Senior Circuit Design Engineer / Physical Design and Integration Consultant
Tue Sep 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Freescale Semiconductor
Senior Design Engineer - Library Development / Integration
Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Magma Design Automation
Senior Applications Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Vitesse Semiconductor
ASIC Design Manager
Tue Jan 01 2002 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
Principal Design Engineer
Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jan 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)
Stmicroelectronics
Memory Design Manager
Sat Jan 01 1994 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)