
Michael Wright
Experienced engineer with over 20 years of turning complex designs and ideas into working solutions. Performed key... | Austin, Texas, United States
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Michael Wright’s Location Austin, Texas, United States
Michael Wright’s Expertise Experienced engineer with over 20 years of turning complex designs and ideas into working solutions. Performed key roles in RTL design and DV for many ASICs and FPGAs, as well as software development for a large-scale, real-time image processing system. Architected a UVM-based testbench environment to test a mobile GPU core at Samsung. Designed the environment to integrate an asynchronously running C++ model simulator and also be able to run with the driver for software testing. Used Python and YAML as the basis for an auto-generated testbench creation flow. Wrote testbenches and tests for the top-level GPU, graphics processing sub-system, interpolator, and ALU datapath units. Assisted with the design and debug of all of the other testbenches. At AMD, lead the verification of the texture module in a mobile GPU core. At Hamilton Sundstrand, lead the verification of 2 FPGAs used in fighter jet engines. Architected and designed several hardware and software components for a 1.45 gigapixel airborne image sensor including image retrieval for video windows, H.264 video compression and JPEG2000 encoding. Wrote software for the supporting ground station to do JPEG2000 decoding. Also architected and designed 2 versions of the ingress traffic manager FPGA in a terabit router. Designed, tested and demonstrated a DVB-S2 modem transmitter, a GPS C/A code receiver and multiple components of 2 commercially successful ATI GPUs including ALUs, color shaders and Z compression and decompression. Specialties: • Hardware Languages: System Verilog, Verilog, VHDL • Software Languages: Multi-threaded C++, C, Python • Verification Methodology: UVM • Verification APIs: DPI, PLI, FLI • Hardware Protocols: AHB, AXI, ASB, Ethernet, Aurora, SRIO • Hardware Design Tools: Xilinx ISE, Synplify Pro, Design Compiler, ModelSim, VCS
Michael Wright’s Current Industry Amd
Michael
Wright’s Prior Industry
Digital Equipment
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Ati Technologies
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Axiowave Networks
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Mayflower Communications
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Amd
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Mit Lincoln Labs Apex Systems
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Mediatek
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Hamilton Sundstrand Cdi
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Bae Sytems
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Samsung
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Marvell Semiconductor
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Work Experience

Amd
Senior Member of Technical Staff
Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Mar 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Marvell Semiconductor
Senior Staff Engineer
Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Dec 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung
Senior Staff Engineer
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jun 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Bae Sytems
Principal SW Engineer
Tue Jun 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Hamilton Sundstrand Cdi
FPGA Verification Engineer
Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Apr 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)
Mediatek
FPGA Verification Engineer
Mon Jun 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Mit Lincoln Labs Apex Systems
FPGA Design Engineer
Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Amd
Senior Hardware Engineer
Sat Oct 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
Mayflower Communications
Senior Hardware Engineer
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time)
Axiowave Networks
Senior FPGA & ASIC Design Engineer
Tue Aug 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Nov 01 2004 00:00:00 GMT+0000 (Coordinated Universal Time)
Ati Technologies
Senior ASIC Engineer
Wed Apr 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)
Digital Equipment
ASIC Verification Engineer
Tue Jul 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Apr 01 1998 00:00:00 GMT+0000 (Coordinated Universal Time)