
Midhun Dinesh
Sr DFT Automation (CAD) Engineer in Intel India Pvt Ltd, Bangalore. Currently working on UPF collateral generation automation... | Bengaluru, Karnataka, India
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Midhun Dinesh’s Emails m.****@in****.com
Midhun Dinesh’s Phone Numbers No phone number available.
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Midhun Dinesh’s Location Bengaluru, Karnataka, India
Midhun Dinesh’s Expertise Sr DFT Automation (CAD) Engineer in Intel India Pvt Ltd, Bangalore. Currently working on UPF collateral generation automation development using Tessent Infrastructure. Experience in multiple domains including ICL/PDL validation using Mentor Tessent, Cross-site POC for IP auto-generation/integration of DFT IPs and subsystems, SoC-level automation system design for SpyGlass CDC, etc. Had experience in setting up/managing Shared Engineering activities for the cross-site new team. Completed M.Tech in VLSI Design from Amrita School of Engineering, Amritapuri Campus. Love to know about new technological advancements. Always like to think out of the box in the easiest way to get things done.
Midhun Dinesh’s Current Industry Intel
Midhun
Dinesh’s Prior Industry
Intel
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Amrita University
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Cognizant
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Intel Labs
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Work Experience

Intel
Eda Tools Hardware Engineer
Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Sr Dft Automation Engineer
Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Dft Tfm Engineer
Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Mar 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Graduate Technical Intern
Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel Labs
Graduate Technical Intern
Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Feb 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Amrita University
M.Tech In Vlsi Design
Thu May 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Aug 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Cognizant
Programmer Analyst
Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Cognizant
Programmer Analyst Trainee
Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Amrita University
B.Tech In Electronics And Communication Engineering
Sun Jun 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Eda Tools Hardware Engineer
— Present