
Minzhen Ren
ASIC physical design engineer with 7 years of experience in implementing low power digital designs from RTL to...
80 Minot Street, Reading, United States
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Minzhen Ren’s Emails [email protected]
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Minzhen Ren’s Location 80 Minot Street, Reading, United States
Minzhen Ren’s Expertise ASIC physical design engineer with 7 years of experience in implementing low power digital designs from RTL to GDSII. Successfully execute multiple tapeouts in 40nm and 0.18um technology nodes for a variety of applications, such as audio codec, power management units and sensors. Extensive work experience in most of the design stages, including synthesis, floorplanning, power planning/routing (UPF/IEEE1801), CTS, signal routing, STA and more. Strong digital logic design and verification background with Verilog/SystemVerilog for SoC/DSP applications.
Minzhen Ren’s Current Industry Nvidia
Minzhen
Ren’s Prior Industry
Hughes Telematics
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Georgia Institute Of Technology
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Texas Instruments
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Analog Devices
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Nvidia
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Work Experience

Nvidia
Senior Physical Design Engineer
Fri Mar 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Analog Devices
ASIC Physical Design Engineer
Sun Sep 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Nov 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Digital Design Engineer
Tue Jan 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Digital Design Engineer
Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Georgia Institute Of Technology
Graduate Teaching Assistant
Thu Sep 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Georgia Institute Of Technology
Undergraduate Research Assistant
Sun Aug 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Hughes Telematics
Engineering Intern
Fri Jan 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat May 01 2010 00:00:00 GMT+0000 (Coordinated Universal Time)