
Mithunrajmohan
• Good at VHDL and VERILOG ,System Verilog,C,C++, Embedded C,Cshell,PERL • Excellent knowledge in FPGA based design,experience in IP core...
Bengaluru, Karnataka, India
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Mithunrajmohan ’s Emails [email protected]
Mithunrajmohan ’s Phone Numbers No phone number available.
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Mithunrajmohan ’s Location Bengaluru, Karnataka, India
Mithunrajmohan ’s Expertise • Good at VHDL and VERILOG ,System Verilog,C,C++, Embedded C,Cshell,PERL • Excellent knowledge in FPGA based design,experience in IP core design for FPGA. • Sound knowledge in embedded system design. • Experience in PSPICE, MPLAB, CCS, Matlab Simulink, Xilinx ISE 14.5, ModelSim. • Knowledge in Proteus software, Dip-trace for PCB layout Design. • Excellent knowledge in electrical drives and control. • Design of speed controller for 1/2 hp DC motor. • Knowledge in Cadence Orcad,schematics of FPGA based embedded system design. • Experiance RTL compilor,Cadance IES • Experiance in Linting(spyglass)
Mithunrajmohan ’s Current Industry Mediatek
Mithunrajmohan
’s Prior Industry
Cec Chengannur
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Radixmicrosystems
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Xilinx
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Ignitarium Technology Solutions
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Samsung R And D Institute India Bangalore
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Mediatek
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Work Experience

Mediatek
Staff Engineer
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Samsung R And D Institute India Bangalore
Staff Engineer -RTL Design
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Samsung R And D Institute India Bangalore
Associative staff engineer-RTL Design
Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Ignitarium Technology Solutions
Project engineer(Design Engineer)
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Xilinx
Verification Engineer
Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Radixmicrosystems
RTL Design engineer
Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
Cec Chengannur
M-TECH student
Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)