Mithunrajmohan

Mithunrajmohan

• Good at VHDL and VERILOG ,System Verilog,C,C++, Embedded C,Cshell,PERL • Excellent knowledge in FPGA based design,experience in IP core...

Bengaluru, Karnataka, India

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Work Experience

Mediatek

Staff Engineer

Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Samsung R And D Institute India Bangalore

Staff Engineer -RTL Design

Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Samsung R And D Institute India Bangalore

Associative staff engineer-RTL Design

Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)

Ignitarium Technology Solutions

Project engineer(Design Engineer)

Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)

Xilinx

Verification Engineer

Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)

Radixmicrosystems

RTL Design engineer

Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Cec Chengannur

M-TECH student

Thu Aug 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)

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