
Mohit Gupta
Experience in ASIC Design Verification and Performance. Presently working at Intel. Previously worked at Qualcomm for 6 years. Internship... | San Francisco, California, United States
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Mohit Gupta’s Emails mo****@sj****.edu
Mohit Gupta’s Phone Numbers No phone number available.
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Mohit Gupta’s Location San Francisco, California, United States
Mohit Gupta’s Expertise Experience in ASIC Design Verification and Performance. Presently working at Intel. Previously worked at Qualcomm for 6 years. Internship Experience at MediaTek and HGST for 1+ years. Programming Skills :- System Verilog, UVM, Verilog RTL, Python, PERL, C, C++. Digital Logic Design :- RTL Design (using Verilog & SystemVerilog), RTL Simulation Synthesis and Gate-Level Netlist generation, Static Timing Analysis (STA). Verification Methodologies using System Verilog :- Assertion-Based, Constrained Random, UVM, Self-checking test bench, Functional Coverage, Object-Oriented Programming concepts (OOP). EDA Tools :- Synopsys - VCS, Design Compiler, GTK Wave, Verdi, DVE Mentor Graphics - QuestaSim, ModelSim Cadence - NC-Verilog, Simvision Xilinx - Xilinx ISE Design Suite Altera - ModelSim-Altera Operating Systems :- Unix/Linux, Macintosh OS X, Windows Protocols :- UART, M-PHY, UNIPRO, AXI, AHB, APB, PCI-e. Computer Architecture & Memory Systems Concepts :- Cache Organization, MSI/MESI Protocol, RISC Processor Pipelining stages, Virtual Memory.
Mohit Gupta’s Current Industry Intel
Mohit
Gupta’s Prior Industry
Pepperlfuchs
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Incise Infotech
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San Jose State University
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Hgst A Western Digital
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Mediatek
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Scalable System Research Labs
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Qualcomm
|
Intel
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Work Experience

Intel
Staff GPU Performance Engineer
Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Qualcomm
Senior GPU Verification Engineer
Sun Nov 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
GPU Verification Engineer
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Nov 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time)
Scalable System Research Labs
ASIC Engineering Intern
Sat Oct 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Mediatek
ASIC Design Engineering Intern
Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Sep 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Instructional Student Assistant (ISA)
Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Hgst A Western Digital
SoC Verification Student Co-op
Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Aug 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Instructional Student Assistant (ISA)
Thu Jan 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri May 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Incise Infotech
ASIC Verification Engineer
Sat Jun 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Jul 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Pepperlfuchs
Product Application Engineer
Wed Aug 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Apr 01 2013 00:00:00 GMT+0000 (Coordinated Universal Time)