
Nayan Bhalani
A proven leader with extensive experience in a broad range of technologies and designs as individual contributor, technical... | Bristol, England, United Kingdom
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Nayan Bhalani’s Emails na****@im****.com
Nayan Bhalani’s Phone Numbers No phone number available.
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Nayan Bhalani’s Location Bristol, England, United Kingdom
Nayan Bhalani’s Expertise A proven leader with extensive experience in a broad range of technologies and designs as individual contributor, technical leader / manager / director. Successfully led/managed multi-disciplinary team spread across multiple countries. Responsible for building and driving team to deliver project on time by setting up strategies and efficient execution. A verification specialist with multifaceted knowledge and hands on experience with the digital and mixed signal verification languages, tools and methodologies with exposure to post-silicon lab bring-up, emulation, and FPGA debug. Proactive, imaginative & self-motivated in order to take on a variety of tasks and challenges, with a desire to succeed. Specialties: Engineering Manager, RISC-V CPU, Project Execution, Verification Manager / Lead, SoC & IP Verification, SystemVerilog, Mixed Signal Verification, UVM, VMM
Nayan Bhalani’s Current Industry Imagination Technologies
Nayan
Bhalani’s Prior Industry
Orpat Telephones
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Clear Centre
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System Solutions
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Mentor Graphics
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Texas Instruments
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Cirrus Logic
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Imagination Technologies
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Work Experience

Imagination Technologies
Director of Engineering, CPU
Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Cirrus Logic
Verification Manager
Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Nov 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Cirrus Logic
Principal Verification Engineer (Manager)
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Sep 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Cirrus Logic
Sr Verification Engineer
Wed Feb 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)
Texas Instruments
Design Engineer
Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)
Mentor Graphics
Summer Project
Sun Jul 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Oct 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time)
System Solutions
Design and Verification Engineer
Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2006 00:00:00 GMT+0000 (Coordinated Universal Time)
Clear Centre
Engineer
Sun Apr 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Feb 01 2003 00:00:00 GMT+0000 (Coordinated Universal Time)
Orpat Telephones
R & D Engineer
Mon Nov 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Apr 01 2001 00:00:00 GMT+0000 (Coordinated Universal Time)