Nirmala Balakrishnan

Nirmala Balakrishnan

San Jose, California, United States

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Work Experience

Tsavorite Scalable Intelligence

HW Verification Leadership @TSI Powering Enterprise AI @Zettascale

Sun Oct 01 2023 00:00:00 GMT+0000 (Coordinated Universal Time) — Present

Luminous Computing

Senior Director, Head of Digital Verification

Mon Aug 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Aug 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time)

Intel

Engineering Manager - Prinicipal Engineer

Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)

Skhynix Memory Solutions

Principal Engineer/Senior Manager

Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)

Violin Memory

Technical Leader, DesignVerification

Fri Jun 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jun 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time)

Cisco Systems

Technical Leader

Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time)

Chameleon Systems I2p Integrated Intellectual Property

Hardware Engineer

Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time) — Sat Jan 01 2000 00:00:00 GMT+0000 (Coordinated Universal Time)

Realchip

R&D Desgin engineer

Wed Jan 01 1997 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jan 01 1999 00:00:00 GMT+0000 (Coordinated Universal Time)

Skills

Languages

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