
Peter Lieber
I love graphs. Let me explain. While reading an article about map rendering, I was struck with the realization... | Colorado Springs, Colorado, United States
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Peter Lieber’s Location Colorado Springs, Colorado, United States
Peter Lieber’s Expertise I love graphs. Let me explain. While reading an article about map rendering, I was struck with the realization that many of my interests stem from graphs. I have been interested in networks, transit, CPU architecture, FPGAs, algorithms, railroads, maps, circuits, Lego, protocols, graph theory, compilers, GIS, data science, HPC, parallel computing, neural networks, machine learning, traveling, history, physics, 3D graphics, art, drawing, visual communication, product development, modeling, procedural generation. I have been working in the protocol analyzer, networking, and storage industries for the last 9 years. Currently, I work as an SAE, supporting storage products. My activities range from building drivers and debugging to hunting down protocol violations to solving hardware failures. I also work with organizations to develop industry standards. Recently, I have nurtured my interest in CPU and GPU architecture by becoming a member of RISC-V International. Specifically, I contribute to the Graphics SIG. I am getting dev tools working for the new vector extension of RISC-V in order to quantify gaps needed for performant execution of graphics workloads, including ISA simulator, compiler, assembler, across both GNU and LLVM projects. The goal is to be able to experiment with possible custom instructions for graphics and ML such as matrix/vector operations. This is very exciting and affords me the opportunity to be creative around an interesting problem. I have worked as a hardware engineer designing networking products. As an architect and on the technical track, I obtained multiple patents. I have designed protocol analyzers for SAS/SATA, PCIe, and NVMe. My focus was on FPGA logic design. In this capacity, I had experience with all phases of the product life-cycle. I like following industry trends, particularly python, graphics cards, FPGA, CPU, and protocols. I have enjoyed being a part of and contributing to standards organizations and workgroups. With my broad understanding and experience, I excel in various roles such as firmware, logic, hardware, and software engineer, sales engineer, product manager, and technical marketing. I enjoy working with people, at the same time (or while) being able to flex my creative muscles to influence roadmaps, architectures, and products. Give me a problem with constraints and I will create a solution. I want to develop good ideas and see them realized in order to make a difference in the world. This is not just a cliche: I want to feel connected to and motivated about the projects and outcomes of my work.
Peter Lieber’s Current Industry Amd
Peter
Lieber’s Prior Industry
Utah State University
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Translux Commercial
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Palc
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Space Dynamics Laboratory
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Brigham Young University
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Serialtek
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Hewlett Packard Enterprise
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Broadcom
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Rv64x
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Risc V International
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Amd
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Work Experience

Amd
Senior Member of Technical Staff
Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Risc V International
Graphics SIG Contributor
Wed Sep 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Rv64x
Open Source Developer - GPU Architecture and Compilers
Mon Mar 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Apr 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Broadcom
R&D Systems Application Engineer
Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Jul 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Hewlett Packard Enterprise
Switch Architect
Wed Feb 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Hewlett Packard Enterprise
Hardware Engineer
Wed Jul 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Serialtek
Hardware/Firmware Engineer
Tue Feb 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time) — Mon Jun 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Brigham Young University
Graduate Student
Sat Aug 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun May 01 2011 00:00:00 GMT+0000 (Coordinated Universal Time)
Space Dynamics Laboratory
Electrical Engineering Assistant
Sun Mar 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jul 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Palc
Consulting Work
Tue Apr 01 2008 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Aug 01 2017 00:00:00 GMT+0000 (Coordinated Universal Time)
Translux Commercial
Electrical Engineer
Tue May 01 2007 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)
Utah State University
Student
Sat Jan 01 2005 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 2009 00:00:00 GMT+0000 (Coordinated Universal Time)